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publication number s29pl-n_00 revision a amendment 4 issue date november 23, 2005 s29pl-n mirrorbit? flash family 29pl256n, s29pl127n, s29pl129n, 256/128/128 mb (16/8/8 m x 16-bit) cmos, 3.0 volt-only simultaneous read/write, page-mode flash memory data sheet preliminary notice to readers: this document indicates states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that a product qualification has been completed, and that initial produc tion has begun. due to the phases of the manufacturing process that require ma intaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technica l specifications.
ii s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary notice on data sheet designations spansion llc issues data sheets with advance info rmation or preliminary designations to advise readers of product information or intended specif ications throughout the product life cycle, includ - ing development, qualification, initial production, and full production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de - sign. the following descriptions of spansion da ta sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion llc is developing one or more spe - cific products, but has not committed any design to production. information presented in a document with this designation is likely to chan ge, and in some cases, development on the prod - uct may discontinue. spansion llc therefore places the followi ng conditions upon advance information content: ?this document contains information on one or more products under development at spansion llc. the information is intended to help you evaluate this product. do not design in this product without con- tacting the factory. spansion llc reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indi cates that the product developm ent has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initia l production, and the subsequent phases in the manufacturing process that occur before full pr oduction is achieved. changes to the technical specifications presented in a preliminary docume nt should be expected while keeping these as - pects of production under consideration. span sion places the following conditions upon preliminary content: ?this document states the current technical specifications regard ing the spansion product(s) described herein. the preliminary status of th is document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturi ng process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifica- tions due to changes in technical specifications.? combination some data sheets will contain a combination of products with different designations (advance in - formation, preliminary, or full production). this type of document will distinguish these products and their designations wherever necessary, typica lly on the first page, the ordering information page, and pages with dc characteristics table and ac erase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designatio n is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incor - rect specification. spansion llc applies the following conditions to documents in this category: ?this document states the current technical specifications regard ing the spansion product(s) described herein. spansion llc deems the products to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. however, typogr aphical or specification corrections, or modifications to the va lid combinations o ffered may occur.? questions regarding these document designations may be directed to your local amd or fujitsu sales office.
publication number s29pl-n_00 revision a amendment 4 issue date november 23, 2005 general description the spansion s29pl-n is the latest generation 3.0-volt pa ge mode read family fabricated using the 110 nm mirrorbit tm flash process technology. these 8-word page-mode flash device s are capable of performing simultaneous read and write operations with zero latency on two separate banks. these de vices offer fast page access times of 25 to 30 ns, with corresponding random access times of 65 ns, 70 ns, and 80 ns respectively, allo wing high speed microprocessors to op- erate without wait states. the s29pl129n device offers the additional feature of dual ch ip enable inputs (ce1# and ce2#) that allow each half of the memory space to be controlled separately. distinctive characteristics architectural advantages ? 32-word write buffer ? dual chip enable inputs (only for s29pl129n) ? two ce# inputs control selection of each half of the memory space ? single power supply operation ? full voltage range of 2.7 ? 3.6 v read, erase, and program operations for battery-powered applications ? voltage range of 2.7 ? 3.1 v valid for pl-n mcp products ? simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in another bank ? zero latency switching from write to read operations ? 4-bank sector architecture with top and bottom boot blocks ? 256-word secured silicon sector region ? up to 128 factory-locked words ? up to 128 customer-lockable words ? manufactured on 0.11 m process technology ? data retention of 20 years typical ? cycling endurance of 100,000 cycles per sector typical hardware features ? wp#/acc (write protect/acceleration) input ?at v il , hardware level protection for the first and last two 32 kword sectors. ?at v ih , allows the use of dyb/ppb sector protection ?at v hh , provides accelerated programming in a factory setting ? dual boot and no boot options ? low v cc write inhibit security features ? persistent sector protection ? a command sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector ? sectors can be locked and unlocked in-system at v cc level ? password sector protection ? a sophisticated sector protection method locks combinations of individual sectors to prevent program or erase operations within that sector using a user defined 64-bit password performance characteristics note: : typical program and erase times assume the following conditions: 25c, 3.0 v v cc , 10,000 cycles; chec kerboard data pattern. s29pl-n mirrorbit? flash family s29pl256n, s29pl127n, s29pl129n, 256/128/128 mb (16/8/8 m x 16-bit) cmos, 3.0 volt-only simultaneous read/write, page-mode flash memory data sheet preliminary read access times (@ 30 pf, industrial temp.) random access time, ns (t acc )657080 page access time, ns (t pacc )253030 max ce# access time, ns (t ce )657080 max oe# access time, ns (t oe )253030 current consumption (typical values) 8-word page read 6 ma simultaneous read/write 65 ma program/erase 25 ma standby 20 a typical program & erase times (typical values) (see note) ty p i ca l wo r d 40 s typical effective word (32 words in buffer) 9.4 s accelerated write buffer program 6 s typical sector erase time (32-kword sector) 300 ms typical sector erase time (128-kword sector) 1.6 s package options s29pl-n vbh064 8.0 x 11.6 mm, 64-ball vbh084 8.0 x 11.6 mm, 84-ball laa064 11 x 13 mm, 64-ball fortified bga 256 ?? 129 ? 127 ??
2 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary contents 1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 input/output descriptions and logic symbols . . . . . . . . . . . . . . . . . . . . . . 7 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 connection diagrams/physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 special handling instructions for fbga package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.2 vbh084, 8.0 x 11.6 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.2.1 connection diagram ? s29pl256n mcp compatible package . . . . . . . . . . . . . . . . . .9 4.2.2 physical dimensions ? vbh084, 8.0 x 11.6 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 vbh064, 8 x 11.6 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.1 connection diagram ? s29pl127n mcp compatible package . . . . . . . . . . . . . . . . . 11 4.3.2 connection diagram ? s29pl129n mcp compatible package . . . . . . . . . . . . . . . . . 12 4.3.3 physical dimensions ? vbh064, 8 x 11.6 mm ? s29pl-n . . . . . . . . . . . . . . . . . . . . . . 13 4.3.4 connection diagram ? s29pl-n fortified ball grid array package . . . . . . . . . . . . . 14 4.3.5 physical dimensions ? laa064, 11 x 13 mm ? s29pl-n . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 mcp look-ahead connection diagram/physical dimensions . . . . . . . . . . . . . . . . . . . . . . . 16 4.4.1 for all page mode mcps comprised of code flash + (p)sram + data flash . . . . . . 16 5 additional resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 6 product overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 device operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1.1 dual chip enable device description and operation (pl129n only) . . . . . . . . . . . 21 7.2 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 7.2.1 non-page random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 7.2.2 page mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 7.3 autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 7.4 program/erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 7.4.1 single word programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 7.4.2 write buffer programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 7.4.3 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 7.4.4 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 7.4.5 erase suspend/erase resume commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4.6 program suspend/program resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 7.4.7 accelerated program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4.8 unlock bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 7.4.9 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.5 simultaneous read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 7.6 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 7.7 hardware reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 7.8 software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 8 advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . 48 8.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 8.2 persistent protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 8.3 dynamic protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 8.4 persistent protection bit lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.5 password protection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.6 advanced sector protection software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.7 hardware data protection methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.7.1 wp# method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.7.2 low v cc write inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.7.3 write pulse glitch protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.7.4 power-up write inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 9 power conservation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 3 preliminary 9.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 9.2 automatic sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 9.3 hardware reset# input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 9.4 output disable (oe#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 10 secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . 56 10.1 factory secured silicon sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 10.2 customer secured silicon sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 7 10.3 secured silicon sector entry and exit command sequences . . . . . . . . . . . . . . . . . . . . . . . .57 11 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 11.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.3 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.4 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 11.5 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.6 v cc power up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.7 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 11.7.1 dc characteristics (v cc = 2.7 v to 3.6 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 11.7.2 dc characteristics (v cc = 2.7 v to 3.1 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 11.8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 11.8.1 read operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 11.8.2 read operation timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 11.8.3 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 11.8.4 erase/program timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 11.8.5 erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 11.8.6 bga ball capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 12 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 12.1 common flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 13 commonly used terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14 revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary ta b l e s table 2.1 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 6.1 pl256n sector and memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6.2 pl127n sector and memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6.3 pl129n sector and memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7.1 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7.2 dual chip enable device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7.3 word selection within a page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7.4 autoselect codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7.5 autoselect entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 table 7.6 autoselect exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 7.7 single word program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 7.8 write buffer program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7.9 sector erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 7.10 chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7.11 erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 7.12 erase resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 table 7.13 program suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 7.14 program resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 7.15 unlock bypass entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 7.16 unlock bypass program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 7.17 unlock bypass reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 7.18 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 7.19 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 8.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 8.2 sector protection schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 10.1 secured silicon sector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 10.2 secured silicon sector entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 10.3 secured silicon sector program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 10.4 secured silicon sector exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 11.1 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 12.1 memory array commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 12.2 sector protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 12.3 cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 12.4 system interface string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 12.5 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 12.6 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 5 preliminary figures figure 2.1 logic symbols ? pl256 n, pl129n, and pl127n ......................................................... 7 figure 4.1 connection diagram ? 84-ball fine -pitch ball grid array (s29pl256n).......................... 9 figure 4.2 physical dimensions ? 84-ball fine-pitch ball grid array (s29pl256n)........................ 10 figure 4.3 connection diagram ? 64-ball fine -pitch ball grid array (s29pl127n) ....................... 11 figure 4.4 connection diagram ? 64-ball fine -pitch ball grid array (s29pl129n) ....................... 12 figure 4.5 physical dimensions ? 64-ball fine-pitch ball grid array (s29pl-n) ...........................................13 figure 4.6 connection diagram ? 64-ball fine-pitch ball grid array (s29pl127n, s29pl256n) ............14 figure 4.7 physical dimensions ? 64-ball fortified ball grid array (s29pl-n)..............................................15 figure 4.8 mcp look-ahead diagram .................................................................................... 16 figure 7.1 single word program operation ............................................................................ 27 figure 7.2 write buffer programming operation ..................................................................... 30 figure 7.3 sector erase operation ........................................................................................ 32 figure 7.4 write operation status flowchart .......................................................................... 39 figure 7.5 simultaneous operation block diagram for s29pl256n and s29pl127n ..................... 43 figure 7.6 simultaneous operation block diagram for s29pl129n ............................................ 44 figure 8.1 advanced sector protection/unprotection ............................................................... 48 figure 8.2 lock register program algorithm........................................................................... 52 figure 11.1 maximum negative overshoot waveform ............................................................... 59 figure 11.2 maximum positive overshoot waveform ................................................................. 59 figure 11.3 test setup ......................................................................................................... 6 0 figure 11.4 input waveforms an d measurement levels ............................................................. 61 figure 11.5 v cc power-up diagram ........................................................................................ 61 figure 11.6 read operation timings ....................................................................................... 64 figure 11.7 page read operation timings ............................................................................... 65 figure 11.8 reset timings..................................................................................................... 65 figure 11.9 program operation timings .................................................................................. 67 figure 11.10 accelerated program timing diagram .................................................................... 67 figure 11.11 chip/sector eras e operation timings ..................................................................... 68 figure 11.12 back-to-back read/write cycle timings ................................................................. 68 figure 11.13 data# polling timings (during embedded algorithms).............................................. 69 figure 11.14 toggle bit timings (d uring embedded algorithms)................................................... 69 figure 11.15 dq2 vs. dq6 ...................................................................................................... 70
6 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 1 ordering information the ordering part number is formed by a valid combination of the following: s29pl 256 n 65 ga w w0 0 packing type 0=tray 2 = 7-inch tape and reel 3 = 13-inch tape and reel model number (v cc range) w0 = 2.7 ? 3.1 v 00 = 2.7 ? 3.6 v temperature range w = wireless (?25c to +85c) i = industrial (?40c to +85c) package type and material fa = fortified bga, lead (pb)-free compliant package ff = fortified bga, lead (pb)-free package ga = very thin fine-pitch mcp-compatible bga, lead (pb)-free compliant package gf = very thin fine-pitch mcp-compatible bga, lead (pb)-free package speed option 65 = 65 ns 70 = 70 ns 80 = 80 ns process technology n = 110 nm mirrorbit? technology flash density 256 = 256 mb 129 = 128 mb (dual ce#) 127 = 128 mb (single ce#) device family s29pl = 3.0 volt-only simultaneous read/write, page mode flash memory valid combinations v io range package type ( note 2 ) base ordering part number speed option package type, material, & temperature range model number packing ty p e s29pl256n 65, 70 gaw, gfw w0 0, 2, 3 ( note 1 ) 2.7 ? 3.1 v vbh 084 8.0 x 11.6 mm 84 -ball mcp-compatible (fbga) s29pl127n s29pl129n vbh 064 8.0 x 11.6 mm 64 -ball mcp-compatible (fbga) s29pl256n, s29pl127n 80 faw, ffw 00 0, 2, 3 ( note 1 ) 2.7 ? 3.6 v laa0 64 11x13 mm 64 -ball (fortified bga) notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading s29 and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in volume for this de vice. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 7 preliminary 2 input/output descriptions and logic symbols ta b l e 2.1 identifies the input and output packag e connections provided on the device. figure 2.1 logic symbols ? pl256n, pl129n, and pl127n table 2.1 input/output descriptions symbol ty p e description a max ? a0 input address bus dq15 ? dq0 i/o 16-bit data inputs/outputs/float ce# input chip enable input oe# input output enable input we# input write enable v ss supply device ground nc not connected pin not connected internally ry/by# output ready/busy output and open drain. when ry/by#= v ih , the device is ready to accept read operations and commands. when ry/by#= v ol , the device is either executing an embedded algorithm or the device is executing a hardware reset operation. v cc supply device power supply reset# input hardware reset pin ce1#, ce2# input chip enable inputs for s29pl129 device 22 16 dq15 ? dq0 a21 ? a0 wp#/acc reset# ce1# oe# we# ry/by# ce2# vcc max +1 16 amax ?a0 wp#/acc reset# ce# oe# we# ry/by# dq15 ? dq0 vcc notes: 1. amax = 23 for the pl256n and 22 for the pl127n. logic symbol ? pl129n logic symbol ? pl256n and pl127n
8 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 3 block diagram notes: 1. ry/by# is an open drain output. 2. a max = a23 (pl256n), a22 (pl127n), a21 (pl129n). 3. pl129n has two ce# pins ce1# and ce2#. v cc v ss state control command register pgm voltage generator v cc detector timer erase voltage generator input/output buffers sector switches chip enable output enable logic y-gating cell matrix address latch y-decoder x-decoder data latch reset# ry/by# (see note) a max ? a3 a2?a0 ce# we# dq15?dq0 oe#
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 9 preliminary 4 connection diagrams/physical dimensions this section contains the i/o designations and package specifications for the s29pl256n. 4.1 special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning meth - ods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. 4.2 vbh084, 8.0 x 11.6 mm 4.2.1 connection diagram ? s29pl256n mcp compatible package notes: 1. top view?balls facing down. 2. recommended for wireless applications figure 4.1 connection diagram ? 84-ball fine-pitch ball grid array (s29pl256n) a7 a3 a2 dq8 dq14 rfu rfu wp#/acc we# a8 a11 c3 c4 c5 c6 c7 c8 a6 rfu rst# rfu a19 a12 a15 d2 d3 d4 d5 d6 d7 d8 d9 a5 a18 ry/by# a20 a9 a13 a21 e2 e3 e4 e5 e6 e7 e8 e9 a1 a4 a17 a10 a14 a22 f2 f3 f4 f7 f8 f9 v ss dq1 a0 dq6 rfu a16 g3 g4 g2 g7 g8 g9 ce# dq0 oe# dq9 dq3 dq4 dq13 dq15 rfu h2 h3 h4 h5 h6 h7 h8 h9 dq10 v cc rfu dq12 dq7 v ss j2 j3 j4 j5 j6 j7 j8 j9 dq2 dq11 rfu dq5 k3 k8 k4 k5 k6 k7 rfu a23 f5 rfu rfu g5 f6 g6 rfu rfu rfu rfu rfu rfu b3 b4 b5 b6 b7 b8 rfu rfu v cc rfu rfu rfu l3 l4 l5 l6 l7 l8 b2 b9 c9 c2 k2 k9 l9 l2 rfu rfu rfu rfu rfu rfu rfu rfu a1 a10 m1 m10 nc nc nc nc reserved fo r future use legend
10 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 4.2.2 physical dimensions ? vbh084, 8.0 x 11.6 mm note: recommended for wi reless applications figure 4.2 physical dimensions ? 84-ball fine-pitch ball grid array (s29pl256n) 3339 \ 16-038.25b notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbh 084 jedec n/a 11.60 mm x 8.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. ball footprint e1 7.20 bsc. ball footprint md 12 row matrix size d direction me 10 row matrix size e direction n 84 total ball count b 0.33 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement (a2-a9, b10-l10, depopulated solder balls m2-m9, b1-l1) bottom view top view side view a1 corner a2 a 10 9 10 ml j k e c 0.05 (2x) (2x) c 0.05 a1 e d 7 ba c ed f hg 8 7 6 5 4 3 2 1 e d1 e1 se 7 b ca c m 0.15 0.08 m 6 0.10 c c 0.08 nx b sd a b c seating plane a1 corner index mark
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 11 preliminary 4.3 vbh064, 8 x 11.6 mm 4.3.1 connection diagram ? s29pl127n mcp compatible package notes: 1. top view?balls facing down. 2. recommended for wireless applications figure 4.3 connection diagram ? 64-ball fine-p itch ball grid array (s29pl127n) h4 h5 h6 h7 h8 h2 g7 g8 g9 f7 f8 f9 e7 e8 e9 d7 d8 d9 c5 h2 h 2 c6 c7 ce1# h3 oe# rfu dq0 c3 a7 a8 we# wp/acc rfu b5 b7 c8 a11 rfu rfu a15 a12 a19 a21 a13 a9 a22 a14 a10 a16 rfu dq6 e6 rfu a20 g4 f4 e4 e5 d5 rst# rfu ry/by# a18 a17 dq1 rfu dq15 dq13 dq4 dq3 dq9 dq7 rfu v cc dq10 g2 g3 f2 f3 e2 e3 d2 d3 a6 a3 a5 a2 a4 a1 v ss a0 dq8 v ss dq12 dq14 dq5 rfu dq11 dq2 l5 l6 rfu rfu a1 nc a10 nc m10 nc m1 nc h2 c4 d4 d6 reserved for future use no connection j4 j6 j7 j8 j9 j2 j3 k3 k4 k5 k6 k7 k8 legend j5
12 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 4.3.2 connection diagram ? s29pl129n mcp compatible package notes: 1. top view?balls facing down. 2. recommended for wireless applications figure 4.4 connection diagram ? 64-ball fine-p itch ball grid array (s29pl129n) h4 h5 h6 h7 h8 h2 g7 g8 g9 f7 f8 f9 e7 e8 e9 d7 d8 d9 c5 h2 h 2 c6 c7 ce1# h3 oe# rfu dq0 c3 a7 a8 we# wp/acc rfu b5 b7 c8 a11 rfu rfu a15 a12 a19 a21 a13 a9 ce2# a14 a10 a16 rfu dq6 e6 rfu a20 g4 f4 e4 e5 d5 rst# rfu ry/by# a18 a17 dq1 rfu dq15 dq13 dq4 dq3 dq9 dq7 rfu v cc dq10 g2 g3 f2 f3 e2 e3 d2 d3 a6 a3 a5 a2 a4 a1 v ss a0 dq8 v ss dq12 dq14 dq5 rfu dq11 dq2 l5 l6 rfu rfu a1 nc a10 nc m10 nc m1 nc h2 c4 d4 d6 reserved for future use no connection j4 j6 j7 j8 j9 j2 j3 k3 k4 k5 k6 k7 k8 legend j5
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 13 preliminary 4.3.3 physical dimensions ? vbh064, 8 x 11.6 mm ? s29pl-n note: recommended for wi reless applications figure 4.5 physical dimensions ? 64-ball fine-pitch ball grid array (s29pl-n) 3330 \ 16-038.25b notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbh 064 jedec n/a 11.60 mm x 8.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. ball footprint e1 7.20 bsc. ball footprint md 12 row matrix size d direction me 10 row matrix size e direction n 64 total ball count b 0.33 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement (a2-9,b1-4,b7-10,c1-k1, depopulated solder balls m2-9,c10-k10,l1-4,l7-10, g5-6,f5-6) bottom view top view side view a1 corner a2 a 10 9 10 ml j k e c 0.05 (2x) (2x) c 0.05 a1 e d 7 ba c ed f hg 8 7 6 5 4 3 2 1 e d1 e1 se 7 b ca c m 0.15 0.08 m 6 0.10 c c 0.08 nx b sd a b c seating plane a1 corner index mark
14 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 4.3.4 connection diagram ? s29pl-n fortified ball grid array package notes: 1. top view?balls facing down. 2. a23 is nc on pl127n. figure 4.6 connection diagram ? 64-ball fine-pitch ball grid array (s29pl127n, s29pl256n) a2 c2 d2 e2 f2 g2 h2 a3 c3 d3 e3 f3 g3 h3 a4 c4 d4 e4 f4 g4 h4 a5 c5 d5 e5 f5 g5 h5 a6 c6 d6 e6 f6 g6 h6 a7 c7 d7 e7 f7 g7 h7 dq15 v ss rfu a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 a21 reset# we# dq11 dq3 dq10 dq2 a20 a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 a1 c1 d1 e1 f1 g1 h1 nc nc rfu nc nc nc nc nc a8 c8 b2 b3 b4 b5 b6 b7 b1 b8 d8 e8 f8 g8 h8 nc nc nc v ss v cc a23 a22 nc
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 15 preliminary 4.3.5 physical dimensions ? laa064, 11 x 13 mm ? s29pl-n note: recommended for automotive applications figure 4.7 physical dimensions ? 64-ball fortified ball grid array (s29pl-n)
16 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 4.4 mcp look-ahead connection diagram/physical dimensions 4.4.1 for all page mode mcps comprised of code flash + (p)sram + data flash notes: 1. f1 and f2 denote xip/code flash, whil e f3 and f4 denote data/companion flash. 2. in addition to being defined as f2-ce#, ball c5 can also be assigned as f1-ce2# for code fl ash that has two chip enable signals. 3. f-v io is rfu on the pl-n product family. figure 4.8 mcp look-ahead diagram j3 oe# c3 v ss d2 rfu d3 a7 d7 a8 d6 we# d8 a11 n-ale# n-pre c6 c6 c 6 c 6 f-v cc or (n-v cc ) c4 rfu e9 a15 e8 a12 e7 a19 f9 f9 a21 f8 f8 a13 f7 f7 a9 h9 a16 h8 a24 h7 dq6 f6 f6 a20 f4 f4 a18 h4 h4 dq1 j9 rfu j8 dq15 j7 dq13 j6 dq4 j5 dq3 j4 dq9 e3 a6 e2 a3 f3 f3 a5 f2 f2 a2 h3 h3 v ss h2 h2 a0 l3 l3 dq8 m2 a27 m3 a26 l8 l8 dq14 l7 l7 dq5 l6 l6 a25 l5 l5 dq11 l4 l4 dq2 m4 v ss rfu c2 m9 rfu nc nc b2 r-lb# d4 nc nc a1 nc nc b9 nc nc b10 nc nc nc nc nc nc nc p2 nc r1-ce2 e6 r-v ccq m7 e4 r-ub# n9 p9 p10 n10 n1 n2 p1 r1-v cc l2 l 2 l2 a1 g2 g2 a4 g3 g3 a17 g4 g4 a23 g6 g6 a10 g7 g7 a14 g8 g8 a22 g9 g9 a9 a10 b1 a2 wp#/acc f2-ce# n-cle n1-ce# f-rst# f-ry/by# f1-ce# k8 k8 dq7 k9 k9 v ss k7 k7 dq12 k4 k4 dq10 k3 k3 dq0 k6 r1-v cc k2 r1-ce1# f-v cc n-wp# l9 f-v cc n2-ce# m6 f-v io d5 d5 c5 c5 e5 e5 f5 f5 j2 j2 k5 k5 m5 m5 m8 m8 r2-ce1# or (n-we#) r2-v cc (or n-v cc ) r2-ce2 or (n-re#) legend: xram shared psram only flash/xram shared flash/data shared rfu (reserved for future use) code flash only x mirrorbit data only x x x x x x x x x x x x x x nand or psram x x x nand x x x g5 g5 g 5 g 5 h5 h5 h 5 h 5 h6 h6 h 6 h 6 c7 c7 c 7 c 7 c8 c8 c 8 c 8 c9 c9 c 9 c 9 d9 d9 d 9 d 9
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 17 preliminary to provide customers with a migrat ion path to higher densities, as well as the option to stack more die in a package, spansion has pr epared a standard pinout that supports: ? nor flash and sram densities up to 4 gb ? nor flash and psram densities up to 4 gb ? nor flash and psram and data storage densities up to 4 gb the signal locations of the resultant mcp device are shown above. note that for different densi - ties, the actual package outline ca n vary. however, any pinout in any mcp is a subset of the pinout shown above. in some cases, there may be outr igger balls in locations outside the grid shown above. in such cases, the user is advised to treat these as rfus, and not connect them to any other signal. in case of any further inquiries about the abov e look-ahead pinout, please see the application note, design-in scalable wireless solutions with spansion products , or contact a spansion sales office.
18 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 5 additional resources visit www.amd.com and www.fujitsu.com to obtain the following related documents: application notes ? using the operation status bits in amd devices ? simultaneous read/write vs. erase suspend/resume ? mirrorbit? flash memory write buffer programming and page buffer read ? design-in scalable wireless solutions with spansion products ? common flash interface version 1.4 vendor specific extensions specification bulletins contact your local sale s office for details. drivers and software support ? spansion low-level drivers ? enhanced flash drivers ? flash file system cad modeling support ? vhdl and verilog ? ibis ? orcad technical support contact your local sales office or contact spansi on llc directly for addi tional technical support: email us and canada: hw.support@amd.com asia pacific: asia.support@amd.com europe, middle east, and africa japan: http://edevice.fujitsu.com/jp/support/tech/#b7 frequently asked questions (faq) http://ask.amd.com/ http://edevice.fujitsu.c om/jp/support/tech/#b7 phone us: (408) 749-5703 japan (03) 5322-3324 spansion llc locations 915 deguigne drive, p.o. box 3453 sunnyvale, ca 94088-3453, usa telephone: 408-962-2500 or 1-866-spansion spansion japan limited 4-33-4 nishi shinjuku, shinjuku-ku tokyo, 160-0023 telephone: +81-3-5302-2200 facsimile: +81-3-5302-2674 http://www.spansion.com
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 19 preliminary 6 product overview the s29plxxxn family co nsists of 256 and 128 mb, 3.0 volts-only, simultaneous read/write page-mode read flash devices that are optimized fo r wireless designs of today that demand large storage array and rich functionality, while requir ing low power consumption. these products also offer 32-word buffer for programming with prog ram and erase suspend/resume functionality. ad - ditional features include: ? advanced sector protection methods for protecti ng an individual or group of sectors as re- quired, ? 256-word of secured silicon area for storin g customer and factory secured information ? simultaneous read/write operation 6.1 memory map the s29pl-n devices consist of 4 banks organized as shown in ta b l e s 6.1 , 6.2 , and 6.3 . note: ellipses indicate that other addresses in sector range follow the same pattern. table 6.1 pl256n sector and memory address map bank bank size sector count sector size (kb) sector/ sector range address range notes a 4 mb 4 64 sa00 000000h-007fffh sector starting address ? sector ending address 64 sa01 008000h-00ffffh 64 sa02 010000h-017fffh 64 sa03 018000h-01ffffh 15 256 sa04 020000h-03ffffh sector starting address - sector ending address (see note) ? ? ? 256 sa018 1e0000h-1fffffh b 12 mb 48 256 sa19 200000h-21ffffh first sector, sector starting address - last sector, sector ending address (see note) ? ? ? 256 sa66 7e0000h-7fffffh c 12 mb 48 256 sa67 800000h-81ffffh first sector, sector starting address - last sector, sector ending address (see note) ? ? ? 256 sa114 de0000h-dfffffh d 4 mb 15 256 sa115 e00000h-e1ffffh sector starting address - sector ending address (see note) ? ? ? 256 sa129 fc0000h-fdffffh 4 64 sa130 fe0000h-fe7fffh sector starting address - sector ending address 64 sa131 fe8000h-feffffh 64 sa132 ff0000h-ff7fffh 64 sa133 ff8000h-ffffffh
20 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary note: ellipses indicate that other addresses in sector range follow the same pattern. table 6.2 pl127n sector and memory address map bank bank size sector count sector size (kb) sector/ sector range address range notes a 2 mb 4 64 sa00 000000h-007fffh sector starting address - sector ending address 64 sa01 008000h-00ffffh 64 sa02 010000h-017fffh 64 sa03 018000h-01ffffh 7 256 sa04 020000h-03ffffh sector starting address ? sector ending address (see note) ? ? ? 256 sa10 0e0000h-0fffffh b 6 mb 24 256 sa11 100000h-11ffffh first sector, sector starting address - last sector, sector ending address (see note) ? ? ? 256 sa34 3e0000h-3fffffh c 6 mb 24 256 sa35 400000h-41ffffh first sector, sector starting address - last sector, sector ending address (see note) ? ? ? 256 sa58 6e0000h-6fffffh d 2 mb 7 256 sa59 700000h-71ffffh sector starting address - sector ending address (see note) ? ? ? 256 sa65 7c0000h-7dffffh 4 64 sa66 7e0000h-7e7fffh sector starting address - sector ending address 64 sa67 7e80000h-7effffh 64 sa68 7f0000h-7f7fffh 64 sa69 7f8000h-7fffffh table 6.3 pl129n sector and memory address map bank bank size sector count sector size (kb) ce1# ce2# sector/ sector range address range notes 1a 2 mb 4 64 v il v ih sa00 000000h-007fffh sector starting address - sector ending address 64 sa01 008000h-00ffffh 64 sa02 010000h-017fffh 64 sa03 018000h-01ffffh 7 256 sa04 020000h-03ffffh sector starting address ? sector ending address (see note) ? ? ? 256 sa10 0e0000h-0fffffh 1b 6 mb 24 256 sa11 100000h-11ffffh first sector, sector starting address - last sector, sector ending address (see note) ? ? ? 256 sa34 3e0000h-3fffffh 2a 6 mb 24 256 v ih v il sa35 000000h-01ffffh first sector, sector starting address - last sector, sector ending address (see note) ? ? ? 256 sa58 2e0000h - 2fffffh 2b 2 mb 7 256 sa59 300000h-31ffffh sector starting address - sector ending address (see note) ? ? ? 256 sa65 3c0000h-3dffffh 4 64 sa66 3e0000h-3e7fffh sector starting address - sector ending address 64 sa67 3e8000h-3effffh 64 sa68 3f0000h-3f7fffh 64 sa69 3f8000h-3fffffh
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 21 preliminary 7 device operations this section describes the read, program, erase, simultaneous read/write operations, and reset features of the flash devices. operations are initiated by writing specific comm ands or a sequence with specific address and data patterns into the command registers (see ta b l e 12.1 and ta b l e 12.2 ). the command regis - ter itself does not occupy any addressable memory location. inst ead, the command register is composed of latches that store the commands, along with the address and data information needed to execute the command. th e contents of the register serve as input to the internal state machine and the state machine ou tputs dictate the function of the device. writing incorrect ad - dress and data values or writing them in an improper sequence can place the device in an unknown state, in which case the system must wr ite the reset command to return the device to the reading array data mode. 7.1 device operation table the device must be setup appr opriately for each operation. ta b l e 7.1 describes the required state of each control pin for any particular operation. legend: l = logic low = v il , h = logic high = v ih , v hh = 8.5 ? 9.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out note: wp#/acc must be high when writing to upper two and lower two sectors (pl256n: 0, 1,132, and 133; pl127/129n: 0, 1, 68, and 69) 7.1.1 dual chip enable device desc ription and operation (pl129n only) the dual ce# product (pl129n) offers a reduce d number of address pins to accommodate pro - cessors with a limited addressable range. this product operates as two separate devices in a single package and requires the processor to addr ess half of the memory space with one chip en - able and the remaining memory space with a second chip enab le. for more details on the addressing features of the dual ce# device refer to ta b l e 6.3 on page 20 for the pl129n sector and memory address map. dual chip enable products must be setup approp riately for each operation. to place the device into the active state either ce1# or ce2# must be set to v il . to place the device in standby mode, both ce1# and ce2# must be set to v ih . ta b l e 7.2 describes the required state of each control pin for any particular operation. table 7.1 device operation operation ce# oe# we# reset# wp#/acc addresses (a max ? a0) dq15 ? dq0 read l l h h x a in d out write l h l h x ( see note ) a in d in standby h x x h x a in high-z output disable l h h h x a in high-z reset x x x l x a in high-z
22 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary legend: l = logic low = v il , h = logic high = v ih ,vid = 11.5?12.5 v, v hh = 8.5 ? 9.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. the sector and sector unprotect functions may also be implemented by programming equipment. 2. wp#/acc must be high when writing to the upper two and lower two sectors. 7.2 asynchronous read the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessa ry in this mode to obtain ar ray data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enable d for read access until th e command register con - tents are altered. 7.2.1 non-page random read address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable addr esses and stable ce# to valid data at the output inputs. the output enable access time is the delay fr om the falling edge of the oe# to valid data at the output (assuming the addresses have been stable for at least t acc ? t oe time). 7.2.2 page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the random or initial page access is t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . when ce# is deasserted (= v ih ), the reassertion of ce# for subs equent access has access time of t acc or t ce . here again, ce# selects the device and oe# is the output control and should be used to gate data to the output inputs if the device is selected. fast page mode accesses are obtained by keeping a max ? a3 constant and changing a2 ? a0 to select the specific word within that page. address bits a max ? a3 select an 8-word page, and address bits a2 ? a0 select a specific word within that page. this is an asynchronous operat ion with the microprocessor supplying the specific word location. see ta b l e 7.3 for details on select ing specific words. table 7.2 dual chip enable device operation operation ce1# ce2# oe# we# reset# wp#/acc addresses (a21 ? a0) dq15 ? dq0 read lh lh h x a in d out hl write lh hl h x ( note 2 ) a in d in hl standby h h x x h x x high-z output disable l l h h h x x high-z reset x x x x l x x high-z temporary sector unprotect (high voltage) xxxx v id x a in d in
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 23 preliminary the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. all addre sses are latched on the fa lling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. reads from the memory array may be performed in conjunction with the erase suspend and pro - gram suspend features. after the device accept s an erase suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non- erase-suspended sector within the same bank. the system can read array da ta using the standard read timing, except that if it reads at an addr ess within erase-suspended sectors, the device out - puts status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. after the device accepts a pro - gram suspend command, the corresponding bank enters the program-suspend-read mode, after which the system can read data from any non-pr ogram-suspended sector within the same bank. 7.3 autoselect the autoselect mode allows the host system to access manufacturer and device identification, and verify sector protection, through identifier co des output from the inte rnal register (separate from the memory array) on dq15-dq0. this mode is primarily intended to allow equipment to automatically match a device to be programmed with its corresponding programming algorithm. when verifying sector protection, the sector a ddress must appear on the appropriate highest order address bits (see ta b l e 7.5 ) . the remaining address bits are don't care. when all necessary bits have been set as required, the programmi ng equipment can then read the corresponding identifier code on dq15-dq0. the autoselect codes can also be accessed in-sys tem through the command register. note that if a bank address (ba) on the four uppermost address bits is asserted during the third write cycle of the autoselect command, the ho st system can read autoselect data from that bank and then immediately read array data from the other bank, without exiting the autoselect mode. ? to access the autoselect codes, the host system must issue the autoselect command. ? the autoselect command sequence can be written to an address within a bank that is either in the read or erase-suspend-read mode. ? the autoselect command cannot be written while the device is actively programming or eras- ing in the other bank. ? autoselect does not support simultan eous operations or page modes. ? the system must write the reset command to return to the read mode (or erase-suspend- read mode if the bank was previously in erase suspend). table 7.3 word selection within a page word a2 a1 a0 word 0 0 0 0 word 1 0 0 1 word 2 0 1 0 word 3 0 1 1 word 4 1 0 0 word 5 1 0 1 word 6 1 1 0 word 7 1 1 1
24 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary see ta b l e 12.1 for command sequence details. legend: l = logic low = v il , h = logic high = v ih , ba = bank address, sa = sect or address, x = don?t care. note: for the pl129n either ce1# or ce2# mu st be low to access autoselect codes notes: 1. any offset within the device works. 2. ba = bank address. the bank address is required. 3. base = base address. the following is a c source code example of using the autoselect function to read the manufac - turer id. see the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. table 7.4 autoselect codes description ce# see note oe# we# a max ? a12 a10 a9 a8 a7 a6 a5 ? a4 a3 a2 a1 a0 dq15 to dq0 manufacturer id l l h ba x x x l l x l l l l 0001h device id: read cycle 1 l lh baxxxlll l l l h 227eh read cycle 2 lhhhl 223ch (pl256n) 2220h (pl127n) 2221h (pl129n) read cycle 3 l hhhh 2200h (pl256n) 2200h (pl127n) 2200h (pl129n) sector protection verification llhsaxxxlllllhl 0000h unprotected (neither dyb nor ppb locked), 0001h protected (either dyb or ppb locked) indicator bit l l h ba x x x l l l l l h h - dq15 - dq8 = 0 - dq7 - factory lock bit 1 = locked, 0 = not locked -dq6 -customer lock bit 1 = locked, 0 = not locked - dq5 - handshake bit 1 = reserved, 0 = standard handshake -dq4 & dq3 - wp# protection boot code 00 = wp# protects both top boot and bottom boot sectors, 11 = no wp# protection -dq2 - dq0 = 0 software functions and sample code table 7.5 autoselect entry (lld function = lld_autoselectentrycmd) cycle operation word address data unlock cycle 1 write bax555h 0x00aah unlock cycle 2 write bax2aah 0x0055h autoselect command write bax555h 0x0090h table 7.6 autoselect exit (lld function = lld_autoselectexitcmd) cycle operation word address data unlock cycle 1 write base + xxxh 0x00f0h
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 25 preliminary /* here is an example of autoselect mode (getting manufacturer id) */ /* define uint16 example: typedef unsigned short uint16; */ uint16 manuf_id; /* auto select entry */ *((uint16 *)bank_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)bank_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)bank_addr + 0x555) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *((uint16 *)bank_addr + 0x000); /* read manuf. id */ /* autoselect exit */ *((uint16 *)base_addr + 0x000) = 0x00f0; /* exit autoselect (write reset command) */
26 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 7.4 program/erase operations these devices are capable of single word or wr ite buffer programming operations which are de - scribed in the following sections. the write buffer programming is recommended over single word programming as it has clear benefits fr om greater programming efficiency. see ta b l e 7.1 on page 21 for the correct device settings required be fore initiation of a write command sequence. note the following details regard ing the program/erase operations: ? when the embedded program algorithm is comp lete, the device then returns to the read mode. ? the system can determine the status of the program operation by using dq7 or dq6. see write operation status for information on these status bits. ? a 0 cannot be programmed back to a 1 . attempting to do so causes the device to set dq5 = 1 (halting any further operation and requirin g a reset command). a succeeding read shows that the data is still 0 . ? only erase operations can convert a 0 to a 1 . ? a hardware reset immediately terminates the program operation and the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. ? any commands written to the device during the embedded program algorithm are ignored except the program suspend command. ? secured silicon sector, autoselect, and cfi f unctions are unavailable when a program oper- ation is in progress. ? programming is allowed in any sequence and ac ross sector boundaries for single word pro- gramming operation. 7.4.1 single word programming in single word programming mode, four flash co mmand write cycles are used to program an in - dividual flash address. while this method is supported by all spansion devices, in general it is not recommended for devices that suppo rt write buffer programming. see ta b l e 12.1 for the re - quired bus cycles and figure 7.1 for the flowchart. when the embedded program algorithm is complete , the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the program oper - ation by using dq7 or dq6. see write operation status for information on these status bits. single word programming is supported for backward compatibility with existing flash driver soft - ware and use of write buffer programming is strongly recommended fo r general programming. the effective word programming time using write buffer programming is approximately four times faster than the single word programming time.
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 27 preliminary figure 7.1 single word program operation note: base = base address. the following is a c source code example of us ing the single word program function. see the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: program command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x00a0; /* write program setup command */ *((uint16 *)pa) = data; /* write data to be programmed */ /* poll for program completion */ software functions and sample code ta b l e 7 . 7 s i n g l e wo r d p r o g r a m (lld function = lld_programcmd) cycle operation word address data unlock cycle 1 write base + 555h 00aah unlock cycle 2 write base + 2aah 0055h program setup write base + 555h 00a0h program write word address data word write unlock cycles: address 555h, data aah address 2aah, data 55h write program command: address 555h, data a0h program data to address: pa, pd unlock cycle 1 unlock cycle 2 setup command program address (pa), program data (pd) fail. issue reset command to return to read array mode. perform polling algorithm (see write operation status flowchart) yes yes no no polling status = busy? polling status = done? error condition (exceeded timing limits) pass. device is in read mode.
28 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 7.4.2 write buffer programming write buffer programming allows the system to write a maximu m of 32 words in one program - ming operation. this results in a faster effe ctive word programming time than the standard word programming algorithms. the writ e buffer programming command se quence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector a ddress in which programming occurs. at this point, the system writes the number of word locations minus 1 that is loaded into the page buffer at the sector ad - dress in which programming occurs. this tells th e device how many write buffer addresses are loaded with data and ther efore when to expect the program buffer to flash confirm command. the number of locations to prog ram cannot exceed the size of th e write buffer or the operation aborts. (number loaded = the number of location s to program minus 1. for example, if the sys - tem programs 6 address locations, then 05h should be written to the device.) the system then writes the starti ng address/data combination. this starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. all subsequent address/data pairs must fall with in the elected-write-buffer-page. the write-buffer-page is selected by using the addresses a max ? a5. the write-buffer-page addresses must be the same for all a ddress/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed across multiple write-buffer- page . this also means that write buffer programmi ng cannot be performed across multiple sec - tors. if the system attempts to load programming data outside of the selected write-buffer-page , the operation aborts .) after writing the starting address/data pair, the system then writes the remaining address/data pairs into the write buffer. note that if a write buffer address lo cation is loaded multiple times, the address/data pair counter decrements for every data load op eration. also, the last data lo aded at a location before the pro - gram buffer to flash confirm command is programmed into the device. the software takes care of the ramifications of loading a write-buffer lo cation more than once. the counter decrements for each data load operation, not for each unique write-buffer-address location. once the speci - fied number of write buffer locations have been loaded, th e system must then write the program buffer to flash command at the sector addr ess. any other address/data write combinations abort the write buffer programming operation. the device then goes busy. the data bar polling tech - niques should be used while monitoring the last ad dress location loaded into the write buffer. this eliminates the need to store an address in memo ry because the system can load the last address location, issue the program confir m command at the last loaded ad dress location, and then data bar poll at that same address. the write-buffer embedded programming operation can be su spended using the standard sus - pend/resume commands. upon succe ssful completion of the write buffer programming operation, the device returns to read mode. if the write buffer comm and sequence is entered incorrectly th e device enters write buffer abort. when an abort occurs the write-to buffer-abort reset command must be issued to return the de - vice to read mode. the write buffer programming sequence is aborted under any of the following conditions: ? load a value that is greater than the page buffer size during the number of locations to pro- gram step. ? write to an address in a sector differe nt than the one specified during the write-buffer-load command. ? write an address/data pair to a different write-buffer-page than the one selected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles.
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 29 preliminary use of the write buffer is stro ngly recommended for programming when multiple words are to be programmed. write buffer programming is approx imately four times faster than programming one word at a time. note that the secured silico n, the cfi functions, and the autoselect codes are not available for read when a write bu ffer programming operation is in progress. notes: 1. base = base address. 2. last = last cycle of write buffer program operation; depend ing on number of words written, the total number of cycles can be from 6 to 37. 3. for maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (n words) possible. the following is a c source code example of us ing the write buffer program function. see the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: write buffer programming command */ /* notes: write buffer programming limited to 16 words. */ /* all addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. a flash page begins at addresses */ /* evenly divisible by 0x20. */ uint16 *src = source_of_data; /* address of source data */ uint16 *dst = destination_of_data; /* flash destination address */ uint16 wc = words_to_program -1; /* word count (minus 1) */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)sector_address) = 0x0025; /* write write buffer load command */ *((uint16 *)sector_address) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* all dst must be same page */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *((uint16 *)sector_address) = 0x0029; /* write confirm command */ /* poll for completion */ /* example: write buffer abort reset */ *((uint16 *)addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)addr + 0x555) = 0x00f0; /* write buffer abort reset */ software functions and sample code table 7.8 write buffer program (lld functions used = lld_writetobuff ercmd, lld_programbuffertoflashcmd) cycle description operation word address data 1 unlock write base + 555h 00aah 2 unlock write base + 2aah 0055h 3 write buffer load command write program address 0025h 4 write word count write program address word count (n?1)h number of words (n) loaded into the wr ite buffer can be from 1 to 32 words. 5 to 36 load buffer word n write program address, word n word n last write buffer to flash write sector address 0029h
30 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary figure 7.2 write buffer programming operation 7.4.3 sector erase the sector erase function erases one or more sectors in the memory array. (see ta b l e 12.1 , and figure 7.3 .) the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire memory for an all zero data pat - tern prior to electrical erase. th e system is not required to provid e any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than t sea occurs. dur - ing the time-out period, additional sector addre sses and sector erase commands can be written. loading the sector erase buffer can be done in any sequence, and the number of sectors can be from one sector to all sectors. the time between these additional cycles must be less than t sea . any sector erase address and command following the exceeded time-out (t sea ) may or may not write unlock cycles: address 555h, data aah address 2aah, data 55h issue write buffer load command: address 555h, data 25h load word count to program program data to address: sa = wc unlock cycle 1 unlock cycle 2 wc = number of words ? 1 yes yes yes yes yes no no no no no wc = 0? write buffer abort desired? write buffer abort? polling status = done? error? fail. issue reset command to return to read array mode. write to a different sector address to cause write buffer abort pass. device is in read mode. confirm command: sa 29h wait 4 s perform polling algorithm (see write operation status flowchart) write next word, decrement wc: pa data , wc = wc ? 1 reset. issue write buffer abort reset command
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 31 preliminary be accepted. any command other than sector eras e or erase suspend during the time-out period resets that bank to the read mode. the system can monitor dq3 to determine if the sector erase timer has timed out ( see dq3: sector erase timeout state indicator ). the time-out begins from the rising edge of the final we # pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and ad - dresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank s. the system can determine the status of the erase operation by reading dq7 or dq6/dq2 in the erasing bank. see write operation status for information on these status bits. once the sector erase operation has begun, only the erase suspen d command is valid. all other commands are ignored. however, note that a ha rdware reset immediately terminates the erase operation. if that occurs, the sector erase comma nd sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 7.3 illustrates the algorithm for the erase operation. see ac characteristics for the erase/ program operations parameters and timing diagrams. the following is a c source code example of using the sector erase function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: sector erase command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x0080; /* write setup command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write additional unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write additional unlock cycle 2 */ *((uint16 *)sector_address) = 0x0030; /* write sector erase command */ software functions and sample code ta b l e 7 . 9 s e c t o r e r a s e (lld function = lld_sectorerasecmd) cycle description operation word address data 1 unlock write base + 555h 00aah 2 unlock write base + 2aah 0055h 3 setup command write base + 555h 0080h 4 unlock write base + 555h 00aah 5 unlock write base + 2aah 0055h 6 sector erase command write sector address 0030h unlimited additional sectors can be selected fo r erase; command(s) must be written within t sea .
32 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary notes: 1. see table 12.1 for erase command sequence. 2. see the section on dq3 for information on the sector erase timeout. figure 7.3 sector erase operation 7.4.4 chip erase command sequence chip erase is a six-bus cycle operation as indicated by ta b l e 12.1 . these commands invoke the embedded erase algorithm, which does not require the system to preprogram prior to erase. the embedded erase algorithm automati cally preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the sy stem is not required to provide any controls or timings during these operations. the command definition tables ( ta b l e 12.1 and ta b l e 12.2 ) show the address and data requirements for the chip erase command sequence. no write unlock cycles: address 555h, data aah address 2aah, data 55h write sector erase cycles: address 555h, data 80h address 555h, data aah address 2aah, data 55h sector address, data 30h write additional sector addresses fail. write reset command to return to reading array. pass. device returns to reading array. wait 4 s perform write operation status algorithm select additional sectors? unlock cycle 1 unlock cycle 2 yes yes yes yes yes no no no no last sector selected? done? dq5 = 1? command cycle 1 command cycle 2 command cycle 3 specify first sector for erasure error condition (exceeded timing limits) status may be obtained by reading dq7, dq6 and/or dq2. poll dq3. dq3 = 1? ? each additional cycle must be written within t sea timeout ? timeout resets after each additional cycle is written ? the host system may monitor dq3 or wait t sea to ensure acceptance of erase commands ? no limit on number of sectors ? commands other than erase suspend or selecting additional sectors for erasure during timeout reset device to reading array data no write unlock cycles: address 555h, data aah address 2aah, data 55h write sector erase cycles: address 555h, data 80h address 555h, data aah address 2aah, data 55h sector address, data 30h write additional sector addresses fail. write reset command to return to reading array. pass. device returns to reading array. wait 4 s perform write operation status algorithm select additional sectors? unlock cycle 1 unlock cycle 2 yes yes yes yes yes no no no no last sector selected? done? dq5 = 1? command cycle 1 command cycle 2 command cycle 3 specify first sector for erasure error condition (exceeded timing limits) status may be obtained by reading dq7, dq6 and/or dq2. poll dq3. dq3 = 1? ? each additional cycle must be written within t sea timeout ? timeout resets after each additional cycle is written ? the host system may monitor dq3 or wait t sea to ensure acceptance of erase commands ? no limit on number of sectors ? commands other than erase suspend or selecting additional sectors for erasure during timeout reset device to reading array data
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 33 preliminary when the embedded erase algorithm is complete, that bank returns to the read mode and ad - dresses are no longer latched. the system can determine the stat us of the erase operation by using dq7 or dq6/dq2. see write operation status for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hard - ware reset immediately terminates the erase oper ation. if that occurs, the chip erase command sequence should be reinitiated once that bank ha s returned to reading array data, to ensure data integrity. the following is a c source code example of using the chip erase function. refer to the span- sion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash me mory software development guidelines. /* example: chip erase command */ /* note: cannot be suspended */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x0080; /* write setup command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write additional unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write additional unlock cycle 2 */ *((uint16 *)base_addr + 0x000) = 0x0010; /* write chip erase command */ 7.4.5 erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is re - quired when writing this command. this command is valid only during the sector erase operation, including the minimum t sea time-out period during the sector erase command sequence. the erase suspend command is ignored if writ ten during the chip erase operation. when the erase suspend command is written duri ng the sector erase operation, the device re - quires a maximum of t esl (erase suspend latency) to susp end the erase operation. however, when the erase suspend command is written duri ng the sector erase time-out, the device imme - diately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the bank enters the er ase-suspend-read mode. the system can read data from or program data to any sector no t selected for erasure. (the de - vice erase suspends all sectors selected for erasure.) reading at any address within erase- suspended sectors produces status information on dq7-dq0. the system can use dq7, or dq6, and dq2 together, to determine if a sector is ac tively erasing or is erase-suspended. refer to ta b l e 7.18 for information on these status bits. software functions and sample code table 7.10 chip erase (lld function = lld_chiperasecmd) cycle description operation word address data 1 unlock write base + 555h 00aah 2 unlock write base + 2aah 0055h 3 setup command write base + 555h 0080h 4 unlock write base + 555h 00aah 5 unlock write base + 2aah 0055h 6 chip erase command write base + 555h 0010h
34 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary after an erase-suspended program operation is co mplete, the bank returns to the erase-suspend- read mode. the system can determ ine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. in the erase-suspend-read mode , the system can also issue th e autoselect command sequence. see write buffer programming and autoselect for details. to resume the sector erase operation, the sy stem must write the er ase resume command. the bank address of the erase-suspended bank is requ ired when writing this command. further writes of the resume command are ignored. another er ase suspend command can be written after the chip has resumed erasing. the following is a c source code example of using the erase suspend function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: erase suspend command */ *((uint16 *)bank_addr + 0x000) = 0x00b0; /* write suspend command */ the following is a c source code example of using the erase resume function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: erase resume command */ *((uint16 *)bank_addr + 0x000) = 0x0030; /* write resume command */ /* the flash needs adequate time in the resume state */ 7.4.6 program suspend/program resume commands the program suspend command allows the system to interrupt an embedded programming op - eration or a write to buffer programming operation so that data can read from any non- suspended sector. when the program suspend co mmand is written during a programming pro - cess, the device halts the pr ogramming operation within t psl (program suspend latency) and updates the status bits. after the programming operation has been suspende d, the system can read array data from any non-suspended sector. the program suspend comman d can also be issued during a programming operation while an erase is suspended. in this ca se, data can be read fr om any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area, then user must use the proper command se quences to enter and exit this region. software functions and sample code table 7.11 erase suspend (lld function = lld _erasesuspendcmd) cycle operation word address data 1 write bank address 00b0h ta b l e 7 . 1 2 e r a s e r e s u m e (lld function = lld_eraseresumecmd) cycle operation word address data 1 write bank address 0030h
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 35 preliminary the system can also write the au toselect command sequence when the device is in program sus - pend mode. the device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory ar ray. when the device exits the autoselect mode, the device re - verts to program suspend mode, and is ready for another valid operation. see autoselect for more information. after the program resume command is written, the device reverts to programming. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status for more information. the system must write the program resume command (address bits are don't cares ) to exit the program suspend mode and contin ue the programming operation. further writes of the program resume command are ignored. another program suspend command can be written after the de - vice has resumed programming. the following is a c source code example of us ing the program suspend function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: program suspend command */ *((uint16 *)base_addr + 0x000) = 0x00b0; /* write suspend command */ the following is a c source code example of using the program resume function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: program resume command */ *((uint16 *)base_addr + 0x000) = 0x0030; /* write resume command */ 7.4.7 accelerated program accelerated single word programming, write buff er programming, sector erase, and chip erase operations are enabled through the acc function. th is method is faster than the standard chip program and erase command sequences. the accelerated chip program and erase functions must not be used more than 10 times per sector. in addition, accelerated chip program an d erase should be performed at room temperature (25 c 10 c). this function is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this input, the device automatica lly enters the aforementioned unlock by - pass mode and uses the higher voltage on the inpu t to reduce the time required for program and erase operations. the system can then use the write buffer load comma nd sequence provided by the unlock bypass mode. note that if a write-to-buffer-abort reset is required while in unlock software functions and sample code table 7.13 program suspend (lld function = lld_programsuspendcmd) cycle operation word address data 1 write bank address 00b0h ta b l e 7 . 1 4 p r o g r a m r e s u m e (lld function = lld_programresumecmd) cycle operation word address data 1 write bank address 0030h
36 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary bypass mode, the full 3-cycle reset command sequ ence must be used to reset the device. re - moving v hh from the acc input, upon completion of the embedded program or erase operation, returns the device to normal operation. ? sectors must be unlocked prior to raising wp#/acc to v hh . ? the wp#/acc must not be at v hh for operations other than accelerated programming and accelerated chip erase, or device damage can result. ? set the acc pin at v cc when accelerated programming not in use. 7.4.8 unlock bypass the device features an unlock bypass mode to facilitate faster word programming. once the de - vice enters the unlock bypass mode, only two writ e cycles are required to program data, instead of the normal four cycles. this mode dispenses with the initial two unlock cy cles required in the st andard program command sequence, resulting in fast er total programming time. ta b l e 12.1, memory array commands shows the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the read, unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode , the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode. the following are c source code examples of using the unlock by pass entry, program, and exit functions. refer to the spansion low level driver user?s guide (available soon on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: unlock bypass entry command */ *((uint16 *)bank_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)bank_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)bank_addr + 0x555) = 0x0020; /* write unlock bypass command */ /* at this point, programming only takes two write cycles. */ /* once you enter unlock bypass mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* unlock bypass mode before beginning a different type of */ /* operations. */ software functions and sample code table 7.15 unlock bypass entry (lld function = lld_unlockbypassentrycmd) cycle description operation word address data 1 unlock write base + 555h 00aah 2 unlock write base + 2aah 0055h 3 entry command write base + 555h 0020h
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 37 preliminary /* example: unlock bypass program command */ /* do while in unlock bypass entry mode! */ *((uint16 *)bank_addr + 0x555) = 0x00a0; /* write program setup command */ *((uint16 *)pa) = data; /* write data to be programmed */ /* poll until done or error. */ /* if done and more to program, */ /* do above two cycles again. */ /* example: unlock bypass exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x0090; *( (uint16 *)base_addr + 0x000 ) = 0x0000; 7.4.9 write operation status the device provides several bits to determine the status of a program or erase operation. the following subsections describe the function of dq1, dq2, dq3, dq5, dq6, and dq7. dq7: data# polling. the data# polling bit, dq7, indicate s to the host system whether an em - bedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command se - quence. note that the data# polling is valid only for the last word being programmed in the write- buffer-page during write buffer programming. re ading data# polling status on any word other than the last word to be programmed in the wr ite-buffer-page returns fa lse status information. during the embedded program algorithm, the de vice outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is comp lete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sect or, data# polling on dq7 is active for approxi - mately t psp , then that bank returns to the read mode. during the embedded erase algori thm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete, or if the bank en ters the erase suspend mode, data# polling pro - duces a 1 on dq7. the system must provide an addr ess within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately t asp , then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. ho wever, if the system reads dq7 at an address within a protected se ctor, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 can change asyn - chronously with dq6 ? dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to vali d data on dq7. depending on when the system table 7.16 unlock bypass program (lld function = lld_unlockbypassprogramcmd) cycle description operation word address data 1 program setup command write base +xxxh 00a0h 2 program command write program address program data table 7.17 unlock bypass reset (lld function = lld_unlockbypassresetcmd) cycle description operation word address data 1 reset cycle 1 write base +xxxh 0090h 2 reset cycle 2 write base +xxxh 0000h
38 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 ha s valid data, the data outputs on dq6 ? dq0 may be still invalid. valid data on dq7 ? dq0 appears on successive read cycles. see the following for more information: ta b l e 7.18, write operation status , shows the outputs for data# polling on dq7. figure 7.4, write operation status flowchart , shows the data# polling algorithm. figure 11.13, data# polling timings (during embedded algorithms) shows the data# polling timing diagram.
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 39 preliminary figure 7.4 write operation status flowchart start read 1 dq7=valid data? yes no read 1 dq5=1? yes no write buffer programming? yes no device busy, re-poll read3 dq1=1? yes no read 2 read 3 read 2 read 3 read 2 read 3 read3 dq1=1 and dq7 valid data? yes no (note 4) write buffer operation failed dq6 toggling? yes no timeout (note 1) (note 3) programming operation? dq6 toggling? yes no yes no dq2 toggling? yes no erase operation complete device in erase/suspend mode program operation failed device error erase operation complete read3= valid data? yes no notes: 1. dq6 is toggling if read2 dq6 does not equal read3 dq6. 2. dq2 is toggling if read2 dq2 does not equal read3 dq2. 3. may be due to an attempt to program a 0 to 1. use the reset command to exit operation. 4. write buffer error if dq1 of last read =1. 5. invalid state, use reset command to exit operation. 6. valid data is the data that is intended to be programmed or all 1's for an erase operation. 7. data polling algorithm valid for all operations except advanced sector protection. device busy, re-poll device busy, re-poll device busy, re-poll (note 1) (note 2) (note 6) (note 5)
40 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary dq6: toggle bit i . toggle bit i on dq6 indicates whether an embedded program or erase algo - rithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i can be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any ad - dress cause dq6 to toggle. when the oper ation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for a pproximately t asp (all sectors protected toggle time), then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro - tected sectors, and ignores the sele cted sectors that are protected. the system can use dq6 and dq2 to gether to determine whether a sector is actively erasing or is erase-suspended. when the device is active ly erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops tog - gling. however, the system must also use dq2 to determine whic h sectors are erasing or erase- suspended. alternatively, the system can use dq7, see dq7: data# polling. if a program address falls within a protec ted sector, dq6 toggles for approximately t pap after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-pr ogram mode, and stops toggling once the embed - ded program algorithm is complete. see the following for ad ditional information: figure 7.4, write operation status flowchart , figure 11.14, toggle bit timings (dur ing embedded algorithms) , ta b l e 7.18, write operation status , and figure 11.15, dq2 vs. dq6 . toggle bit i on dq6 requires either oe# or ce# to be de-asserted and reasserted to show the change in state. dq2: toggle bit ii . the toggle bit ii on dq2, when used with dq6, indicates whether a partic - ular sector is actively erasing (that is, the em bedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the ri sing edge of the final we# pulse in the command sequence. dq2 toggl es when the system reads at addresses within those sectors that have been selected for erasure. but dq2 ca nnot distinguish whether the sector is actively erasing or is erase-suspended. dq 6, by comparison, indicates whether the device is actively eras - ing, or is in erase suspend, but cannot distingu ish which sectors are selected for erasure. thus, both status bits are required for se ctor and mode information. refer to ta b l e 7.18, write opera - tion status to compare outputs for dq2 and dq6. see the following for additional information: figure 7.4, write operation status flowchart and figure 11.14, toggle bit timings (during em - bedded algorithms) . reading toggle bits dq6/dq2. whenever the system initially be gins reading toggle bit status, it must read dq7 ? dq0 at least twice in a row to determine whether a toggle bit is toggling. typ - ically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed th e program or erases operation. the system can read array data on dq7 ? dq0 on the following read cycle. howe ver, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then deter - mine again whether the toggle bit is toggling, si nce the toggle bit might have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully com - pleted the program or erases operation. if it is still toggling, the device did not complete the operation successfully, and the syst em must write the reset command to return to reading array data. the remaining scenario is that the system init ially determines that the toggle bit is toggling and dq5 has not gone high. the system may cont inue to monitor the toggle bit and dq5 through
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 41 preliminary successive read cycles, determining the status as described in the previous paragraph. alterna - tively, it can choose to perform other system tasks. in this case , the system must start at the beginning of the algorithm when it returns to determine the status of the operation. refer to figure 7.4, write operation status flowchart for more details. dq5: exceeded timing limits. dq5 indicates whether the progra m or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 , indicating that the program or erase cycle was not successfu lly completed. the device may output a 1 on dq5 if the system tries to program a 1 to a location that was previously programmed to 0 . only an erase operation can change a 0 back to a 1 , under this condition, the de vice halts the operation, and when the timing limit has been exceeded, dq5 produces a 1 . under both these conditions, the system must write the reset comm and to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase time out state indicator. after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each addi tional sector erase command. when the time-out period is complete, dq3 switches from a 0 to a 1 . if the time between ad ditional sector erase commands from the system can be assumed to be less than t sea , the system need not monitor dq3. see sector erase command sequence for more details. after the sector erase command is written, the system should read the status of dq7 (data# poll - ing) or dq6 (toggle bit i) to ensure that th e device has accepted the command sequence, and then read dq3. if dq3 is 1 , the embedded erase algorithm has begun; all further commands (ex - cept erase suspend) are ignored until the erase operation is complete. if dq3 is 0 , the device accepts additional sector erase commands. to ensure the command has been accepted, the sys - tem software should check the status of dq3 prio r to and following each sub-sequent sector erase command. if dq3 is high on th e second status check, the last command might not have been accepted. ta b l e 7.18 shows the status of dq3 relati ve to the other status bits. dq1: write to buffer abort. dq1 indicates whether a write to buffer operation was aborted. under these conditions dq1 produces a 1 . the system must issue the write to buffer abort reset command sequence to return th e device to reading array data . see write buffer programming operation for more details.
42 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary notes: 1. dq5 switches to ?1? when an embedde d program or embedded erase operation ha s exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 a valid address when reading status information. refer to the appropriate subsection for further details. 3. data are invalid for addresses in a program suspended sector. 4. dq1 indicates the write to buffer abort status during write buffer programming operations. 5. the data-bar polling algorithm should be used for write buffer programming oper ations. note that dq7# during write buffer programming indicates the data-bar for dq7 data for the last loaded write-buffer address location . table 7.18 write operation status status dq7 ( note 2 ) dq6 dq5 ( note 1 ) dq3 dq2 ( note 2 ) dq1 ( note 4 ) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle n/a program suspend mode ( note 3 ) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) reading within non-program suspended sector data data data data data data erase suspend mode erase-suspend-read erase suspended sector 1 no toggle 0 n/a toggle n/a non-erase suspended sector data data data data data data erase-suspend-program dq7# toggle 0 n/a n/a n/a erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle n/a non-erase suspended sector data data data data data data erase-suspend-program dq7# toggle 0 n/a n/a n/a write to buffer ( note 5 ) busy state dq7# toggle 0 n/a n/a 0 exceeded timing limits dq7# toggle 1 n/a n/a 0 abort state dq7# toggle 0 n/a n/a 1
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 43 preliminary 7.5 simultaneous read/write the simultaneous read/write featur e allows the host system to re ad data from one bank of mem - ory while programming or erasing another bank of memory. an erase operation may also be suspended to read from or program another loca tion within the same bank (except the sector being erased). figure 11.12, back-to-back read /write cycle timings shows how read and write cycles may be initiated for simultaneous op eration with zero latency. see the table, dc charac - teristics for read-while-program and read-w hile-erase current specifications. note: a max = a23 (pl256n), a22 (pl127n) figure 7.5 simultaneous operation block diagram for s29pl256n and s29pl127n v cc v ss bank a address bank b address a max ? a0 reset# we# ce# dq0 ? dq15 state control and command register ry/by# bank a x-decoder oe# dq15 ? dq0 status control a max ?a0 a max ? a0 a max ? a0 a max ?a0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 mux mux mux bank b x-decoder y-gate bank c x-decoder bank d x-decoder y-gate bank c address bank d address wp#/acc
44 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary figure 7.6 simultaneous operation block diagram for s29pl129n v cc v ss bank 1a address bank 1b address a21 ? a0 reset# we# ce1# dq0 ? dq15 ce2# state control and command register ry/by# bank 1a x-decoder oe# status control a21 ? a0 a21 ? a0 a21 ? a0 a21 ? a0 dq15 ? dq0 dq15 ? dq0 dq15 ? dq0 dq15 ? dq0 dq15 ? dq0 mux mux mux bank 1b x-decoder y-gate bank 2a x-decoder bank 2b x-decoder y-gate bank 2a address bank 2b address ce1# = l ce2# = h ce1# = h ce2# = l wp#/acc
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 45 preliminary 7.6 writing commands /command sequences during a write operation, the syst em must drive ce# and we# to v il and oe# to v ih when pro - viding an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising ed ge of we# or ce#. an erase operation can erase one sector, multiple sector s, or the entire device. ta b l e 6.1 and ta b l e 6.2 indicate the address space that each sector occupies. the device addr ess space is divided into four banks: banks b and c contain only 128 kword sect ors, while banks a and d contai n both 32 kword boot sectors in addition to 12 8 kword sectors. a bank address is the set of address bits required to uniquely select a bank. similarly, a sector address is the address bits required to uniquely select a sector. i cc2 in dc characteristics represents the active current specification for the write mode. see ac characteristics contains timing specification tables and timing diagrams for write operations.
46 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 7.7 hardware reset the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the reset# pulse. the device also resets th e internal state machine to reading array data. to ensure data integrity the operation that was in terrupted should be reinitiated once the device is ready to accept another command sequence. when reset# is held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby current is greater. reset# may be tied to the system reset circuitr y which enables the system to read the boot-up firmware from the flash memory upon a system reset. see figure 11.5 and figure 11.8 for timing diagrams. 7.8 software reset software reset is part of the command set (see ta b l e 12.1 ) that also returns the device to array read mode and must be used for the following conditions: 1. to exit autoselect mode 2. to reset software when dq5 goes high during write status operation that indicates program or erase cycle was not successfully completed 3. to exit sector lock/unlock operation. 4. to return to erase-suspend-read mode if the device was previously in erase suspend mode. 5. to reset software after any aborted operations note: base = base address. the following is a c source code example of using the reset function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: reset (software reset of flash state machine) */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; the following are additional points to consider when using the reset command: ? this command resets the banks to the read and address bits are ignored. ? reset commands are ignored once erasure ha s begun until the operation is complete. ? once programming begins, the device ignore s reset commands until the operation is com- plete ? the reset command may be written between the cycles in a program command sequence be- fore programming begins (prior to the third cycle). this resets the bank to which the system was writing to the read mode. ? if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? the reset command may be also written during an autoselect command sequence. software functions and sample code ta b l e 7 . 1 9 r e s e t (lld function = lld_resetcmd) cycle operation word address data reset command write base + xxxh 00f0h
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 47 preliminary ? if a bank has entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? if dq1 goes high during a write buffer prog ramming operation, the system must write the write to buffer abort reset command sequence to reset the device to reading array data. the standard reset command does not work during this condition. ? to exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset com- mand sequence (see command tables for detail).
48 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 8 advanced sector protection/unprotection the advanced sector protection/u nprotection feature disables or enables programming or erase operations in any or all sectors and can be im plemented through software and/or hardware meth - ods, which are independent of each other. th is section describes the various methods of protecting data stored in the memory array. an overview of these methods in shown in figure 8.1 . figure 8.1 advanced sector protection/unprotection hardware methods software methods wp# = v il (all boot sectors locked) password method (dq2) persistent method (dq1) lock register (one time programmable) ppb lock bit ( notes 1, 2, 3 ) 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n (note 4) ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppd) ( notes 5, 6 ) dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (dyb) (notes 7, 8, 9) notes: 1. bit is volatile, and defaults to 1 on reset. 2. programming to 0 locks all ppbs to their current state. 3. once programmed to 0, requires hardware reset to unlock. 4. n = highest address sector. 5. 0 = sector protected, 1 = sector unprotected. 6. ppbs programmed individually, but cleared collectively. 7. 0 = sector protected, 1 = sector unprotected. 8. protect effective only if ppb lock bit is unlocked and corresponding ppb is 1 (unprotected). 9. volatile bits: defaults to user choice upon power-up (see ordering options).
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 49 preliminary 8.1 lock register as shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the dyb ordering option (see or - dering information ). the device programmer or host system must then choose which sector protection method to use. programming (setting to 0 ) any one of the following two one-time pro - grammable, non-volatile bits locks the part permanently in that mode: ? lock register persistent protection mode lock bit (dq1) ? lock register password protection mode lock bit (dq2) for programming lock register bits see ta b l e 12.2 . notes 1. if the password mode is chosen, the password must be programmed before setting the cor- responding lock register bit. 2. after the lock register bits command set entry command sequence is written, reads and writes for bank a are disabled, while reads fr om other banks are allowed until exiting this mode. 3. if both lock bits are selected to be progra mmed (to zeros) at the same time, the operation aborts. 4. once the password mode lock bit is programmed, the persistent mode lock bit is perma- nently disabled, and no change s to the protection scheme ar e allowed. similarly, if the persistent mode lock bit is programmed, the password mode is permanently disabled. after selecting a sector protection method, each sector can operat e in any of the following three states: 1. constantly locked. the selected sectors are protected and cannot be reprogrammed unless ppb lock bit is cleared via a password, hardware reset, or power cycle. 2. dynamically locked. the selected sectors are protected and can be altered via software commands. 3. unlocked. the sectors are unprotected and can be erased and/or programmed. these states are controlled by the bit types described in sections 8.2 ? 8.6 . 8.2 persistent protection bits the persistent protection bits are unique and no nvolatile for each sector and have the same en - durances as the flash memory. preprogramming an d verification prior to erasure are handled by the device, and therefore do no t require system monitoring. table 8.1 lock register device dq15 ? 05 dq4 dq3 dq2 dq1 dq0 s29pl256n undefined dyb lock boot bit 0 = sectors power up protected 1 = sectors power up unprotected ppb one-time programmable bit 0 = all ppb erase command disabled 1 = all ppb erase command enabled password protection mode lock bit persistent protection mode lock bit secured silicon sector protection bit
50 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary notes 1. each ppb is individually programmed and all are erased in parallel. 2. entry command disables reads and writes for the bank selected. 3. reads within that bank return the ppb status for that sector. 4. reads from other banks are allowe d while writes are not allowed. 5. all reads must be performed using the asynchronous mode. 6. the specific sector addresses (a23 ? a14 pl 256n and a22 ? a14 pl127n/pl129n) are writ- ten at the same time as the program command. 7. if the ppb lock bit is set, the ppb progra m or erase command does not execute and times- out without programming or erasing the ppb. 8. there are no means for individually erasing a sp ecific ppb and no specific sector address is required for this operation. 9. exit command must be issued after the execut ion which resets the device to read mode and re-enables reads and writes for bank a. 10. the programming state of the ppb for a given sector can be verified by writing a ppb status read command to the device as de scribed by the flow chart below. 8.3 dynamic protection bits dynamic protection bits are volat ile and unique for each sector an d can be individually modified. dybs only control the protection scheme for unprotected sectors that have their ppbs cleared (erased to 1 ). by issuing the dyb set or clear command sequences, the dybs are set (pro - grammed to 0 ) or cleared (erased to 1 ), thus placing each sector in the protected or unprotected state respectively. this feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy remova l of protection when changes are needed. notes 1. the dybs can be set (programmed to 0 ) or cleared (erased to 1 ) as often as needed. when the parts are first shipped, the ppbs are cleared (erased to 1 ) and upon power up or re- set, the dybs can be set or cleared depe nding upon the ordering option chosen. 2. if the option to clear the dybs after power up is chosen, (erased to 1 ), then the sectorsmay be modified depending upon the ppb state of that sector. 3. the sectors would be in the protected state if the option to set the dybs after power up is chosen (programmed to 0 ). 4. it is possible to have sectors that are persiste ntly locked with sectors that are left in the dynamic state. 5. the dyb set or clear commands for the dyna mic sectors signify protected or unprotected state of the sectors respectively. however, if th ere is a need to change the status of the per- sistently locked sectors, a few more steps ar e required. first, the ppb lock bit must be cleared by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired settin gs. setting the ppb lock bit once again locks the ppbs, and the device operates normally again. 6. to achieve the best protection, it is recomm ended to execute the ppb lock bit set command early in the boot code and protect the boot code by holding wp# = v il . note that the ppb and dyb bits have the same function when wp#/acc = v hh as they do when wp#/ acc = v ih . 8.4 persistent protection bit lock bit the persistent protection bit lock bit is a global volatile bit for all sectors. when set (programmed to 0 ), this bit locks all ppb and when cleared (programmed to 1 ), unlocks each sector. there is only one ppb lock bit per device.
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 51 preliminary notes 1. no software command sequence unlocks this bit unless the device is in the password pro- tection mode; only a hardware reset or a power-up clears this bit. 2. the ppb lock bit must be set (programmed to 0 ) only after all ppbs are configured to the desired settings. 8.5 password protection method the password protection method allows an even high er level of security than the persistent sector protection mode by requiring a 64 -bit password for unlocking the devi ce ppb lock bit. in addition to this password requirement, after power up and reset, the ppb lock bit is set 0 to maintain the password mode of operation. successful executio n of the password unlock command by entering the entire password clears the ppb lock bi t, allowing for sect or ppbs modifications. notes 1. there is no special addressing order required for programming the password. once the password is written and verified, the password mode locking bit must be set to prevent ac- cess. 2. the password program command is only capable of programming 0 s. programming a 1 after a cell is programmed as a 0 results in a time-out with the cell as a 0 . 3. the password is all 1 s when shipped from the factory. 4. all 64-bit password combinations are valid as a password. 5. there is no means to verify what the password is after it is set. 6. the password mode lock bit, once set, preven ts reading the 64-bit password on the data bus and further password programming. 7. the password mode lock bit is not erasable. 8. the lower two address bits (a1 ? a0) are valid during the password read, password pro- gram, and password unlock. 9. the exact password must be entered in or der for the unlocking function to occur. 10. the password unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit co mbinations in an atte mpt to correctly match a password. 11. approximately 1 s is required for unlocking the device after the valid 64-bit password is given to the device. 12. password verification is only allowed during the password programming operation. 13. all further commands to the password region are disabled and all operations are ignored. 14. if the password is lost after setting the password mode lock bit, there is no way to clear the ppb lock bit. 15. entry command sequence must be issued prior to any of any operation and it disables reads and writes for bank a. reads and writes fo r other banks excludin g bank a are allowed. 16. if the user attempts to program or erase a protected sector, the device ignores the com- mand and returns to read mode. 17. a program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. 18. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing individual status read commands dyb status , ppb status, and ppb lock status to the device.
52 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary figure 8.2 lock register program algorithm write unlock cycles: address 555h, data aah address 2aah, data 55h write enter lock register command: address 555h, data 40h program lock register data address xxxh, data a0h address 77h*, data pd unlock cycle 1 unlock cycle 2 xxxh = address don?t care * not on future devices program data (pd): see text for lock register definitions caution: lock data may only be progammed once. wait 4 s pass. write lock register exit command: address xxxh, data 90h address xxxh, data 00h device returns to reading array. perform polling algorithm (see write operation status flowchart) yes yes no no done? dq5 = 1? error condition (exceeded timing limits) fail. write rest command to return to reading array.
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 53 preliminary 8.6 advanced sector prot ection software examples ta b l e 8.2 contains all possible combinat ions of the dyb, ppb, and ppb lock bit relating to the sta - tus of the sector. in summary, if th e ppb lock bit is locked (set to 0 ), no changes to the ppbs are allowed. the ppb lock bit can only be unlocked (reset to 1 ) through a hardware reset or power cycle. see also figure 8.1 for an overview of the advanc ed sector protection feature. 8.7 hardware data protection methods the device offers data protection at the sector level via hardware control: ? when wp#/acc is at v il , the four outermost sectors are locked (device specific). there are additional methods by which intended or accidental er asure of any sectors can be pre - vented via hardware means. the follow ing subsections describes these methods: 8.7.1 wp# method the write protect feature provides a hardware meth od of protecting the four outermost sectors. this function is provided by the wp#/acc pin and overrides the previously discussed sector pro - tection/unprotection method. if the system asserts v il on the wp#/acc pin, the device di sables program and erase functions in the outermost boot sectors. the outermost boot sect ors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. if the system asserts v ih on the wp#/acc pin, the device re verts to whether the boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. note that the wp#/acc pin must not be left floati ng or unconnected as inconsistent behavior of the device may result. the wp#/acc pin must be held stable during a command sequence execution 8.7.2 low v cc write inhibit when v cc is less than v lko , the device does not accept any writ e cycles. this protects data during v cc power-up and power-down. the command register and all inte rnal program/erase circuits are disabled, and the device resets to reading array data. subseque nt writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent uninten tional writes when v cc is greater than v lko . table 8.2 sector protection schemes unique device ppb lock bit 0 = locked, 1 = unlocked sector ppb 0 = protected 1 = unprotected sector dyb 0 = protected 1 = unprotected sector protection status any sector 0 0 x protected through ppb any sector 0 0 x protected through ppb any sector 0 1 1 unprotected any sector 0 1 0 protected through dyb any sector 1 0 x protected through ppb any sector 1 0 x protected through ppb any sector 1 1 0 protected through dyb any sector 1 1 1 unprotected
54 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 8.7.3 write pulse glitch protection noise pulses of less than 3 ns (typical) on oe#, ce# or we# do not initiate a write cycle. 8.7.4 power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device does not accept com - mands on the rising edge of we#. the internal state machine is automatically reset to the read mode on powerup.
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 55 preliminary 9 power conservation modes 9.1 standby mode when the system is not reading or writing to th e device, it can place the device in the standby mode. in this mode, current cons umption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# in put. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard ac - cess time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in dc characteristics represents the standb y current specification 9.2 automatic sleep mode the automatic sleep mode minimizes flash device energy consumption while in asynchronous mode. the device automatically enables this mode when addresses remain stable for t acc + 20 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when a ddresses are changed. while in sleep mode, out - put data is latched and always available to the system. i cc6 in dc characteristics represents the automatic sleep mode current specification. 9.3 hardware reset# input operation the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates al l outputs, resets the configuration register, and ignores all read/ write commands for the du ration of the reset# pulse. the devi ce also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current is greater. reset# may be tied to the system reset circuitr y and thus, a system reset would also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. 9.4 output disable (oe#) when the oe# input is at v ih , output from the device is disabl ed. the outputs are placed in the high impedance state.
56 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 10 secured silicon sect or flash memory region the secured silicon sector provides an extra fl ash memory region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 words in length that consists of 128 words for factory data and 128 words for customer-secured areas. all secured silicon reads outside of the 256-word address range returns invalid data. the factory indicator bit, dq7, (at autoselect address 03h) is used to indica te whether or not the factory se - cured silicon sector is locked when shipped from the factory. the customer indicator bit (dq6) is used to indicate whether or not the customer secured silicon sector is locked when shipped from the factory. note the following general conditions: ? while the secured silicon sector access is enab led, simultaneous operations are allowed ex- cept for bank a. ? on power up, or following a hardware reset, th e device reverts to sending commands to the normal address space. ? reads outside of sector 0 return memory array data. ? sector 0 is remapped from the memory array to the secured silicon sector array. ? once the secured silicon sector entry command is issued, the secured silicon sector exit command must be issued to exit secured silicon sector mode. ? the secured silicon sector is no t accessible when the device is executing an embedded pro- gram or embedded erase algorithm. 10.1 factory secured silicon sector the factory secured silicon sector is always pr otected when shipped from the factory and has the factory indicator bit (dq7) permanently set to a 1 . this prevents cloning of a factory locked part and ensures the security of the esn and cust omer code once the prod uct is shipped to the field. these devices are available pre prog rammed with one of the following: ? a random, 8-word secure esn only with in the factory secured silicon sector ? customer code within the customer secu red silicon sector through the spansion tm program- ming service. ? both a random, secure esn and customer code through the spansion programming service. customers may opt to have thei r code programmed through the spansion programming services. spansion programs the customer's code, with or without the random esn. the devices are then shipped from the spansion factory with the fact ory secured silicon sector and customer secured silicon sector permanently locked. contact your lo cal representative for details on using spansion programming services. table 10.1 secured silicon sector addresses sector sector size address range customer 128 words 000080h-0000ffh factory 128 words 000000h-00007fh
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 57 preliminary 10.2 customer secured silicon sector the customer secured silicon sector is ty pically shipped unprotected (dq6 set to 0 ), allowing customers to utilize that sector in any manner they choose. if the security feature is not required, the customer secured silicon sector can be tr eated as an additional flash memory space. please note the following: ? once the customer secured silicon sector area is protected, the customer indicator bit is permanently set to 1 . ? the customer secured silicon sector can be read any number of times, but can be pro- grammed and locked only once. the customer secu red silicon sector lock must be used with caution as once locked, there is no procedur e available for unlocking the customer secured silicon sector area and none of the bits in th e customer secured silicon sector memory space can be modified in any way. ? the accelerated programming (acc) and unlock bypass functions are not available when pro- gramming the customer secured silicon sector , but are available when reading in banks b through d. ? once the customer secured silicon sector is lo cked and verified, the system must write the exit secured silicon sector region command se quence which return the device to the mem- ory array at sector 0. 10.3 secured silicon sector en try and exit command sequences the system can access the secured silicon sector region by issuin g the three-cycle enter secured silicon sector command sequence. the device co ntinues to access the secured silicon sector re - gion until the system issues the four-cycle exit secured silicon se ctor command sequence. see the command definition tables ta b l e 12.1, memory array commands . ta b l e 12.2, sector protection commands for address and data requ irements for both command sequences. the secured silicon sector entry command allows the following commands to be executed ? read customer and factory secured silicon areas ? program the customer secured silicon sector after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresse s normally occupied by sector sa0 within the memory array. this mode of operation continues until the system issues the exit secured silicon sector command sequence, or until power is removed from the device. the following are c functions and source code examples of using the secured silicon sector entry, program, and exit commands. refer to the spansion low level driver user guide (available soon on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. software functions and sample code
58 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary note: base = base address. /* example: secsi sector entry command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x0088; /* write secsi sector entry cmd */ note: base = base address. /* once in the secsi sector mode, you program */ /* words using the programming algorithm. */ note: base = base address. /* example: secsi sector exit command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x0090; /* write secsi sector exit cycle 3 */ *((uint16 *)base_addr + 0x000) = 0x0000; /* write secsi sector exit cycle 4 */ table 10.2 secured silicon sector entry (lld function = lld_secsisectorentrycmd) cycle operation word address data unlock cycle 1 write base + 555h 00aah unlock cycle 2 write base + 2aah 0055h entry cycle write base + 555h 0088h table 10.3 secured silicon sector program (lld function = lld_programcmd) cycle operation word address data unlock cycle 1 write base + 555h 00aah unlock cycle 2 write base + 2aah 0055h program setup write base + 555h 00a0h program write word address data word table 10.4 secured silicon sector exit (lld function = lld_secsisectorexitcmd) cycle operation word address data unlock cycle 1 write base + 555h 00aah unlock cycle 2 write base + 2aah 0055h exit cycle write base + 555h 0090h
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 59 preliminary 11 electrical specifications 11.1 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to + 125c voltage with respect to ground: all inputs and i/os except as noted below ( note 1 ). . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v io + 0.5 v v cc ( note 1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +4.0 v v io ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0v acc ( note 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +10.5 v output short circuit current ( note 3 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. duri ng voltage transitions, inputs or i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 11.1 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 11.2 . 2. minimum dc input voltage on pin wp# ? acc is ?0.5 v. during voltage transitions, wp# ? acc may overshoot v ss to 2.0 v for periods of up to 20 ns. see figure 11.1 . maximum dc voltage on pin wp# ? acc is +9.5 v, which may overshoot to 10.5 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this da ta sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 11.1 maximum negative overshoot waveform figure 11.2 maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
60 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 11.2 operating ranges wireless (w) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?25c to +85c industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c supply voltages v cc supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.7 v to 3.1 v or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 v to +3.6 v ( note 3 ) notes: 1. operating ranges define those limits between whic h the functionality of the device is guaranteed. 2. for all ac and dc specifications, v io = v cc . 3. voltage range of 2.7 ? 3.1 v valid for pl-n mcp products. 11.3 test conditions figure 11.3 te s t s e t u p 11.4 key to switching waveforms table 11.1 test specifications test condition all speeds unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times v cc = 3.0 v 5 ns input pulse levels v cc = 3.0 v 0.0 ? 3.0 v input timing measurement reference levels v cc /2 v output timing measurement reference levels v cc /2 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) c l device under test
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 61 preliminary 11.5 switching waveforms figure 11.4 input waveforms and measurement levels 11.6 v cc power up notes: 1. v cc ramp rate must exceed 1 v/400 s. 2. v io is internally connected to v cc . figure 11.5 v cc power-up diagram parameter description test setup speed unit t vcs v cc setup time min 250 s t read time between reset# high and ce# low min 200 ns v io 0.0 v output measurement level input v cc /2 v cc /2 all inputs and outputs v cc reset# t vcs t read ce# v cc min v ih
62 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 11.7 dc characteristics 11.7.1 dc characteristics (v cc = 2.7 v to 3.6 v) (cmos compatible) notes: 1. the i cc current listed is typically less than 5 ma/mhz, with oe# at v ih . 2. maximum i cc specifications ar e tested with v cc = v cc max, t a = t a max. typical i cc specifications are with typical v cc =3.0 v, t a = +25c. 3. i cc is active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc +30 ns. typical sleep mode current is 1 a. 5. not 100% tested. 6. the data in the table is for v cc range 2.7 v to 3.6 v (recommend ed for standalone applications). 7. ce1# and ce2# for the pl129n. parameter symbol parameter description (notes) test conditions min ( note 2 ) ty p ( note 2 ) max unit i li input load current v in = v ss to v cc , v cc = v cc max ( 6 )2.0a i lo output leakage current v out = v ss to v cc , oe# = v ih v cc = v cc max ( 6 ) 1.0 a i cc1 v cc active read current ( 1 , 3 ) oe# = v ih , v cc = v cc max ( 1 , 6 ) 5 mhz 30 45 ma i cc2 v cc active write current ( 3 )oe# = v ih , we# = v il 25 50 ma i cc3 v cc standby current ce# ( 7 ), reset#, wp#/acc = v cc 0.3 v 20 40 a i cc4 v cc reset current reset# = v ss 0.3 v 300 500 a i cc5 automatic sleep mode ( 4 )v ih = v cc 0.3 v; v il = v ss 0.3 v 20 40 a i cc6 v cc active read-while-write current ( 1 ) oe# = v ih 5 mhz 35 50 ma i cc7 v cc active program-while-erase- suspended current ( 5 ) oe# = v ih 27 55 ma i cc8 v cc active page read current oe# = v ih , 8 word page read 40 mhz 610ma v il input low voltage v cc = 2.7 to 3.6 v ?0.5 0.8 v v ih input high voltage v cc = 2.7 to 3.6 v 2.0 v cc + 0.3 v v hh voltage for acc program acceleration v cc = 3.0 v 10% ( 6 )8.59.5v v ol output low voltage i ol = 100 a, v cc = v cc min ( 6 )0.1v v oh output high voltage i oh = ?100 a ( 6 )v cc ? 0.2 v v lko low v cc lock-out voltage ( 5 )2.32.5v
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 63 preliminary 11.7.2 dc characteristics (v cc = 2.7 v to 3.1 v) (cmos compatible) notes: 1. the i cc current listed is typically less than 5 ma/mhz, with oe# at v ih . 2. maximum i cc specifications ar e tested with v cc = v cc max, t a = t a max. typical i cc specifications are with typical v cc =2.9 v, t a = +25c. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enable s the low power mode when ad dresses remain stable for t acc + 30 ns. typical sleep mode current is 1 a. 5. not 100% tested. 6. data in table is for v cc range 2.7 v to 3.1 v (recommended for mcp applications) 7. ce1# and ce2# for the pl129n. parameter symbol parameter description (notes) test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max ( 6 )2a i lo output leakage current v out = v ss to v cc , oe# = v ih v cc = v cc max ( 6 ) 1 a i cc1 v cc active read current ( 1 , 2 ) oe# = v ih , v cc = v cc max ( 1 , 6 ) 5 mhz 28 40 ma i cc2 v cc active write current ( 2 , 3 )oe# = v ih , we# = v il 22 40 ma i cc3 v cc standby current ( 2 ) ce# ( 7 ), reset#, wp#/acc = v cc 0.3 v 20 40 a i cc4 v cc reset current ( 2 ) reset# = v ss 0.3 v 300 500 a i cc5 automatic sleep mode ( 2 , 4 )v ih = v cc 0.3 v; v il = v ss 0.1 v 20 40 a i cc6 v cc active read-while-write current ( 1 , 2 ) oe# = v ih 5 mhz 33 45 ma i cc7 v cc active program-while-erase- suspended current ( 2 , 5 ) oe# = v ih 24 45 ma i cc8 v cc active page read current ( 2 ) oe# = v ih , 8 word page read 40 mhz 6 9 ma v il input low voltage v cc = 2.7 to 3.6 v ?0.5 0.8 v v ih input high voltage v cc = 2.7 to 3.6 v 2.0 v cc + 0.3 v v hh voltage for acc program acceleration v cc = 3.0 v 10% ( 6 )8.59.5v v ol output low voltage i ol = 100 a, v cc = v cc min ( 6 )0.1v v oh output high voltage i oh = ?100 a ( 6 )v cc ? 0.2 v v lko low v cc lock-out voltage ( 5 )2.32.5v
64 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 11.8 ac characteristics 11.8.1 read operations notes: 1. not 100% tested. 2. see figure 11.3 and table 11.1 for test specifications 3. measurements performed by placing a 50 ohm te rmination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . 4. for 70pf output load capacitanc e, 2 ns is added to the above t acc ,t ce ,t pacc ,t oe values for all speed grades 5. ce1# and ce2# for the pl129n. 11.8.2 read operation timing diagrams figure 11.6 read operation timings parameter description (notes) te s t s e t u p speed options jedec std. 65 70 80 unit t avav t rc read cycle time ( 1 ) min 65 70 80 ns t avqv t acc address to output delay ce#, oe# = v il max 65 70 80 ns t elqv t ce chip enable to output delay ( 5 ) oe# = v il max 65 70 80 ns t pacc page access time max 25 30 30 ns t glqv t oe output enable to output delay max 25 30 30 ns t ehqz t df chip enable to output high z ( 3 )max16ns t ghqz t df output enable to output high z ( 1 , 3 )max16ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first ( 3 ) min 5 ns t oeh output enable hold time ( 1 ) read min 0 ns toggle and data# polling min 10 ns t oh t ce data we# addresses ce# oe# high z valid data high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 65 preliminary figure 11.7 page read operation timings 11.8.3 hardware reset (reset#) note: not 100% tested. figure 11.8 reset timings parameter description all speed options unit jedec std. t rp reset# pulse width min 30 s t rh reset high time before read ( see note )min200ns same page addresses a 22 to a 3 output t ce t acc aa aa+1 aa+2 aa+3 aa+4 aa+5 aa+6 aa+7 t oe t oeh t pacc high-z t oh da da+1 da+2 da+7 t df da+3 da+4 da+5 da+6 t oh t oh t oh t oh t oh t oh t oh t pacc t pacc t pacc t pacc t pacc t pacc a 2 to a 0 ce# oe# we# reset# t rp ce#, oe# t rh
66 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 11.8.4 erase/program timing notes: 1. not 100% tested. 2. in program operation timing, addresses are latched on the falling edge of we#. 3. see program/erase operations for more information. 4. does not include the preprogramming time. parameter description (notes) speed options unit jedec std 65 70 80 t avav t wc write cycle time ( 1 ) min 65 70 80 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low du ring toggle bit polling min 15 ns t wlax t ah address hold time min 35 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 10 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 40 ns t whdl t wph write pulse width high min 25 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation typ 40 s t whwh1 t whwh1 accelerated programming operation typ 24 s t whwh2 t whwh2 sector erase operation typ 1.6 sec t vhh v hh rise and fall times min 250 ns t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns t wep noise pulse margin on we# max 3 ns t sea sector erase accept time-out max 50 s t esl erase suspend latency max 20 s t psl program suspend latency max 20 s t asp toggle time during sector protection typ 100 s t psp toggle time during programming within a protected sector typ 1 s
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 67 preliminary note: pa = program address, pd = program data, d out is the true data at the program address figure 11.9 program operation timings figure 11.10 accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa wp#/acc t vhh v hh v il or v ih v il or v ih t vhh
68 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary note: sa = sector address (for sect or erase), va = valid address for reading status data (see write operation status ) figure 11.11 chip/sector erase operation timings figure 11.12 back-to-back read/write cycle timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch status d out t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t as t rc t ce t ah valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w t as
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 69 preliminary note: va = valid address. illustration shows first status cycle af ter command sequence, last status read cycle, and array data read cycle figure 11.13 data# polling timings (during embedded algorithms) note: va = valid address; not required for dq6. illustration sh ows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 11.14 toggle bit timings (during embedded algorithms) we# ce# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by#
70 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary note: dq2 toggles only when read at an address within an er ase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 11.15 dq2 vs. dq6 11.8.5 erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25c, 3.0 v v cc , 10,000 cycles. additionally, programming typicals assume checkerboard pattern. all values are subject to change. 2. under worst case conditions of 90c, v cc = 2.7 v, 100,000 cycles. all values are subject to change. 3. the typical chip programming time is considerably less th an the maximum chip programmi ng time listed, since most bytes program faster than th e maximum program times listed. 4. in the pre-programming step of the embedded erase al gorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time re quired to execute the two- or four-bus -cycle sequence for the program command. see table 12.1 and table 12.2 for further information on command definitions. 6. contact the local sales office for minimum cycling endurance values in specific applicatio ns and operating conditions. 7. see application note erase suspend/resume timing for more details. 8. word programming specification is based upon a single word programming operation not utilizing th e write buffer. parameter (notes) device condition ty p ( note 1 ) max ( note 2 ) unit comments (notes) sector erase time 128 kword v cc 1.6 7 s excludes 00h programming prior to erasure ( 4 ) acc 1.6 7 32 kword v cc 0.3 4 acc 0.3 4 chip erase time v cc 202 (pl256n) 100 (pl127n) 100(pl129n) 900 (pl256n) 450 (pl127n) 450 (pl129n) s acc 130 (pl256n) 65 (pl127n) 65 (pl129n) 512 (pl256n) 256 (pl127n) 256 (pl129n) word programming time v cc 40 400 s excludes system level overhead ( 5 ) acc 24 240 effective word programming time utilizing program write buffer v cc 9.4 94 s acc 6 60 total 32-word buffer programming time v cc 300 3000 s acc 192 1920 chip programming time using 32-word buffer ( 3 ) v cc 157.3 (pl256n) 78.6 (pl127n) 78.6 (pl129n) 315 (pl256n) 158 (pl127n) 158 (pl129n) s excludes system level overhead ( 5 ) acc 100 (pl256n) 50 (pl127n) 50 (pl129n) 200 (pl256n) 100 (pl127n) 100 (pl129n) erase suspend/erase resume <20 s program suspend/program resume <20 s enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 71 preliminary 11.8.6 bga ball capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 7 10 pf c out output capacitance v out = 0 8 12 pf c in2 control pin capacitance v in = 0 8 11 pf
72 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 73 preliminary 12 appendix this section contains information relating to soft ware control or interfacing with the flash device. for additional information and assistance regarding software, see additional resources , or ex - plore the web at www.amd.com and www.fujitsu.com . table 12.1 memory array commands command sequence (notes) cycles bus cycles (notes 1 ? 6 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read ( 7 )1rard reset ( 8 )1xxxf0 auto- select ( 9 ) manufacturer id 4 555 aa 2aa 55 [ba]555 90 [ba]x00 0001 device id ( 10 ) 6 555 aa 2aa 55 [ba]555 90 [ba]x01 227e [ba]x0e ( note 10 ) [ba]x0f 2200 indicator bits 4 555 aa 2aa 55 [ba]555 90 [ba]x03 ( note 11 ) program 4 555 aa 2aa 55 555 a0 pa data write to buffer ( 17 ) 6 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset ( 17 ) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend ( 14 ) 1 ba b0 program/erase resume ( 15 )1ba30 cfi query ( 16 ) 1 [ba]555 98 unlock bypass mode unlock bypass entry 3 555 aa 2aa 55 555 20 unlock bypass program ( 12 , 13 )2xxa0papd unlock bypass sector erase ( 12 , 13 )2 xx 80 sa 30 unlock bypass erase ( 12 , 13 ) 2 xx 80 xxx 10 unlock bypass cfi ( 12 , 13 )1ba98 unlock bypass reset 2 xx 90 xxx 00 secured silicon sector command definitions secured silicon sector secured silicon sector entry ( 18 ) 3 555 aa 2aa 55 555 88 secured silicon sector program 2 xx a0 pa data secured silicon sector read 1 ra data secured silicon sector exit ( 19 ) 4 555 aa 2aa 55 555 90 xx 00 legend: x = don?t care. ra = read address. rd = read data. pa = address of the memory locati on to be programmed. addresses latch on the falling edge of th e we# or ce# pu lse whichever happens later. pd = program data. data latches on the rising edge of we# or ce# pulse, whichever occurs first. sa = sector address. pl127/129n = a22 ? a15; pl256n = a23 ? a15. ba = bank address. pl256n = a23 ? a21; pl127n = a22 ? a20; pl127n = a21 ? a20. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see ( table 7.1 ) for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bu s cycles are write cycle: read cycle, fourth through sixth cycles of the autoselect commands, fourth cycle of the password verify command, and any cycle reading at rd(0) and rd(1). 4. data bits dq15 ? dq8 are don? t care in command sequences, except for rd, pd, wd, pwd, and pwd3 ? pwd0. 5. unless otherwise noted, these address bits are don?t cares: pl127: a22 ? a15; 129n: a21 ? a15; pl256n: a23 ? a14. 6. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7. no unlock or command cycles required when bank is reading array data. 8. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is prov iding status information) or performing sector lock/unlock. 9. the fourth cycle of the autosele ct command sequence is a read cycle. the system must prov ide the bank address. see autoselect . 10. device ids: pl256n = 223ch; pl127n = 2220h; pl129n = 2221h. 11. see autoselect . 12. the unlock bypass command sequen ce is required prior to this command sequence. 13. the unlock bypass reset comman d is required to return to reading array data when the bank is in the unlock bypass mode. 14. the system may read and prog ram in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 15. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 16. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 37.
74 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary table 12.2 sector protection commands command sequence (notes) cycles bus cycles (notes 1 ? 6 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data lock register command set definitions lock register lock register command set entry ( 25 ) 3 555 aa 2aa 55 555 40 lock register bits program ( 26 ) 2xx a0 00 data lock register bits read 100 data lock register command set exit ( 27 ) 2xx 90 xx 00 password protection command set definitions password password protection command set entry ( 25 ) 3 555 aa 2aa 55 555 60 password program 2xx a0 00/01 02/03 pwd0/ pwd1/ pwd2/ pwd3 password read 4 00 pwd0 01 pwd1 02 pwd2 03 pwd3 password unlock 7 00 25 00 03 00 pwd001 pwd1 02pwd203pwd300 29 password protection command set exit ( 27 ) 2xx 90 xx 00 non-volatile sector protection command set definitions ppb non-volatile sector protection command set entry ( 25 ) 3 555 aa 2aa 55 [ba]555 c0 ppb program 2xx a0[ba]sa00 all ppb erase ( 22 ) 2xx 80 00 30 ppb status read 1[ba]sard(0) non-volatile sector protection command set exit ( 27 ) 2xx 90 xx 00 global non-volatile sector protection freeze command set definitions ppb lock bit global volatile sector protection freeze command set entry ( 25 ) 3 555 aa 2aa 55 555 50 ppb lock bit set 2xx a0 xx 00 ppb lock bit status read 1bard(0) global volatile sector protection freeze command set exit ( 27 ) 2xx 90 xx 00 volatile sector protection command set definitions dyb volatile sector protection command set entry ( 25 ) 3 555 aa 2aa 55 [ba]555 e0 dyb set 2xx a0[ba]sa00 dyb clear 2xx a0[ba]sa01 dyb status read 1[ba]sard(0) volatile sector protection command set exit ( 27 ) 2xx 90 xx 00 17. command sequence resets device for next command after write- to-buffer operation. 18. entry commands are needed to enter a specific mode to enable instructions only availa ble within that mode. 19. the exit command must be issued to reset the device into read mode. otherwise the device hangs. 20. the following mode cannot be performed at the same time. autoselect/cfi/unlock bypa ss/secured silicon. command sequence resets devi ce for next command after write-to-buffer operation. 21. command is valid when device is ready to read array data or when device is in autoselect mode. address equals 55h on all future devices, but 555h for pl256n. 22. requires entry command sequence prior to execution. secured silicon sector exit re set command is required to exit this mode; device may otherwise be placed in an unknown state. legend: x = don?t care ra = read address. rd = read data. pa = address of the memory locati on to be programmed. addresses latch on the falling edge of th e we# or ce# pu lse whichever happens later. pd = program data. data latches on the rising edge of we# or ce# pulse, whichever occurs first. sa = sector address. pl127/129n = a22 ? a15; pl256n = a23 ? a15 ba = bank address. pl256n = a23 ? a21; pl127n = a22 ? a20; pl127n = a21 ? a20. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. pwd3 ? pwd0 = password data. pd3 ? pd0 present four 16 bit combinations that represent the 64-bit password rd(0) = dq0 protection indicator bit. if protected, dq0 = 0, if unprotected, dq0 = 1.
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 75 preliminary 12.1 common flash memory interface the common flash interface (cfi) sp ecification outlines device and host system software inter - rogation handshake, which allows specific vendor -specified soft-ware algo rithms to be used for entire families of devices. software support ca n then be device-independent, jedec id-indepen - dent, and forward- and back-ward-compatible fo r the specified flash device families. flash vendors can standardize their existing in terfaces for long-term compatibility. this device enters the cfi quer y mode when the system writes the cfi query command, 98h, to address (ba)555h any time the device is ready to read array data. the system can read cfi in - formation at the addresses given in tables 12.3 ? 12.6 ) within that bank. all reads outside of the cfi address range, within the bank, return non- valid data. reads from other banks are allowed, writes are not. to terminate reading cfi data , the system must writ e the reset command. the following is a c source code example of us ing the cfi entry and exit functions. refer to the spansion low level driver user?s guide (available at www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: cfi entry command */ *((uint16 *)bank_addr + 0x555) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *((uint16 *)bank_addr + 0x000) = 0x00f0; /* write cfi exit command */ notes: 1. see ( table 7.1 ) for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bu s cycles are write cycle: read cycle, fourth through sixth cycles of the autoselect commands, and password verify commands, and any cycle reading at rd(0) and rd(1). 4. data bits dq15 ? dq8 are don? t care in command sequences, except for rd, pd, wd, pwd, and pwd3 ? pwd0. 5. unless otherwise noted, these address bits are don?t cares: pl127: a22 ? a15; 129n: a21 ? a15; pl256n: a23 ? a14. 6. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7. no unlock or command cycles required when bank is reading array data. 8. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is prov iding status information) or performing sector lock/unlock. 9. the fourth cycle of the autosele ct command sequence is a read cycle. the system must provide the bank address. see autoselect . 10. the data is 0000h for an unlocked sector and 0001h for a locked sector. 11. device ids: pl256n = 223ch; pl127n = 2220h; pl129n = 2221h. 12. see autoselect . 13. the unlock bypass command sequen ce is required prior to this command sequence. 14. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode.the system may read and pr ogram in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 15. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 16. command is valid when device is ready to read array data or when device is in autoselect mode.the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 37. 17. the entire four bus-cycle sequ ence must be entered for which portion of the password. 18. the unlock bypass reset comman d is required to return to reading array data when the ba nk is in the unlock bypass mode.the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 19. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 20. command is valid when device is ready to read array data or when device is in autoselect mode.the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 37. 21. the entire four bus-cycle sequ ence must be entered for which portion of the password. 22. the all ppb erase command pre-programs all ppbs before erasure to prevent over-erasure of ppbs. 23. wp#/acc must be at vhh during the entire operation of this command. 24. command sequence resets devi ce for next command after write- to-buffer operation. 25. entry commands are needed to enter a specific mode to enable instructions only availa ble within that mode. 26. if both the persistent protection mode locking bit and the password protection mode lockin g bit are set a the same time, the command operation aborts and returns the device to the default persistent sector protection mode. 27. the exit command must be issued to reset the device into read mode. otherwise the device hangs.
76 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary for further information, please see the cfi spec ification (see jedec publications jep137-a and jesd68.01and cfi publication 100). please cont act your sales office for copies of these documents. table 12.3 cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string qry 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 12.4 system interface string addresses data description 1bh 0027h v cc min. (write/erase) d7 ? d4: volt, d3 ? d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7 ? d4: volt, d3 ? d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0006h typical timeout per single byte/word write 2 n s 20h 0009h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000bh typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0003h max. timeout for byte/word write 2 n times typical 24h 0003h max. timeout for buffer write 2 n times typical 25h 0002h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) table 12.5 device geometry definition addresses data description 27h 0019h (pl256n) 0018h (pl127n) 0018h (pl129n) device size = 2 n byte 28h 29h 0001h 0000h flash device interface descrip tion (see cfi publication 100) 2ah 2bh 0006h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0003h 0000h 0000h 0001h erase block region 1 information (see the cfi specificatio n or cfi publication 100) 31h 007dh (pl256n) 003dh (pl127n) 003dh (pl129n) erase block region 2 information (see the cfi specificatio n or cfi publication 100) 32h 33h 34h 0000h 0000h 0004h 35h 36h 37h 38h 0003h 0000h 0000h 0001h erase block region 3 information (see the cfi specificatio n or cfi publication 100)
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 77 preliminary table 12.6 primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string pri 43h 0031h major version number , ascii (reflects modifications to the silicon) 44h 0034h minor version number, ascii (reflects modifications to the cfi table) 45h 0010h address sensitive unlock (bits 1 ? 0) 0 = required, 1 = not required silicon technology (bits 5 ? 2) 0100 = 0.11 m 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0008h (pl-n) sector protect/unprotect scheme 01 =29f040 mode, 02 = 29f016 mode, 03 = 29f400 mode, 04 = 29lv800 mode 07 = new sector protect mode, 08 = advanced sector protection 4ah 0073h (pl256n) 003bh (pl127n) 003bh (pl129n) simultaneous operation 00 = not supported, x = number of sectors except bank a 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0002h (pl-n) page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7 ? d4: volt, d3 ? d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7 ? d4: volt, d3 ? d0: 100 mv 4fh 0001h top/bottom boot sector flag 00h = no boot, 01h = dual boot device, 02h = bottom boot device, 03h = top boot device 50h 0001h program suspend 0 = not supported, 1 = supported 51h 0001h unlock bypass 00 = not supported, 01=supported 52h 0007h secured silicon sector (customer otp area) size 2 n bytes 53h 000fh hardware reset low time-out during an embedded algorithm to read mode maximum 2 n ns 54h 000eh hardware reset low time-out not during an embedded algorithm to read mode maximum 2 n ns 55h 0005h erase suspend time-out maximum 2 n s 56h 0005h program suspend time-out maximum 2 n s 57h 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h 0013h (pl256n) 000bh (pl127n) 000bh (pl129n) bank a region information. x = number of sectors in bank 59h 0030h (pl256n) 0018h (pl127n) 0018h (pl129n) bank 1 region information. x = number of sectors in bank 5ah 0030h (pl256n) 0018h (pl127n) 0018h (pl129n) bank 2 region information. x = number of sectors in bank 5bh 0013h (pl256n) 000bh (pl127n) 000bh (pl129n) bank 3 region information. x = number of sectors in bank
78 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 13 commonly used terms term definition acc acc elerate. a special purpose input signal which allows for faster programming or erase operation when raised to a specified voltage above v cc . in some devices acc may protect all sectors when at a low voltage. a max most significant bit of the address input [a 23 for 256 mbit, a22 for 128 mbit, a21 for 64 mbit] a min least significant bit of the address input si gnals (a0 for all devices in this document). asynchronous operation where signal relationships are based only on propagation delays and are unrelated to synchronous control (clock) signal. autoselect read mode for obtaining manufacturer and device information as well as sector protection status. bank section of the memory array consisting of multiple consecutive sectors. a read operation in one bank, can be independen t of a program or erase operation in a different bank for devices that offer simultaneous read and write feature. boot sector smaller size sectors located at the top and or bottom of flash device address space. the smaller sector size allows for finer gra nularity control of erase and protection for code or parameters used to initiate system operation after power on or reset. boundary location at the beginning or end of series of memory locations. burst read see synchronous read . byte 8 bits cfi common flash interface. a flash memory industry standard specification [jedec 137- a and jesd68.01] designed to allow a system to interrogate the flash to determine its size, type and other performance parameters. clear zero (logic low level) configuration register special purpose register wh ich must be programmed to enable synchronous read mode continuous read synchronous method of burst read whereby the device reads continuously until it is stopped by the host, or it has reached the highest address of the memory array, after which the read address wraps around to the lowest memory array address erase returns bits of a flash memory array to their default state of a logical one (high level). erase suspend/erase resume halts an erase operation to allow reading or programming in any sector that is not selected for erasure bga ball grid array package. spansion llc offers two variations: fortified ball grid array and fine-pitch ball grid array. see the specific package drawing or connection diagram for further details. linear read synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with or without wraparound before requiring a new initial address . mcp multi-chip product. a method of combining integrated circuits in a single package by stacking multiple die of the same or different devices. memory array the programmable area of the product available for data storage. mirrorbit? technology spansion? trademarked technology for storing multiple bits of data in the same transistor. page group of words that may be accessed more rapidly as a group than if the words were accessed individually.
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 79 preliminary page read asynchronous read operation of several words in which the first word of the group takes a longer initial access time and su bsequent words in the group take less page access time to be read. different words in the group are accessed by changing only the least significant address lines. password protection sector protection method which uses a programmable password, in addition to the persistent protection method, for protection of sectors in the flash memory device . persistent protection sector protection method that uses commands and only the standard core voltage supply to control protection of sectors in the flash memory device. this method replaces a prior technique of requiring a 12v supply to control the protection method. program stores data into a flash memory by selectively clearing bits of the memory array to leave a data pattern of ones and zeros . program suspend/program resume halts a programming operation to read data from any location that is not selected for programming or erase. read host bus cycle that causes the flash to output data onto the data bus. registers dynamic storage bits for holdin g device control information or tracking the status of an operation. secured silicon an area consisting of 256 by tes in which any word may be programmed once, and the entire area may be protected once from any future programming. information in this area may be programmed at the factory or by the user. once programmed and protected there is no way to change the secured information. this area is often used to store a software readable identification such as a serial number. sector protection use of one or more control bits per sector to indicate whether each sector may be programmed or erased. if the protection bit for a sector is set the embedded algorithms for program or erase ignore the program or erase commands related to that sector. sector an area of the memory array in which all bi ts must be erased together by an erase operation. simultaneous operation mode of operation in which a host system may issue a program or erase command to one bank, that embedded al gorithm operation may then proceed while the host immediately follows the embe dded algorithm command with reading from another bank. reading may continue concurrently in any bank other than the one executing the embedded algorithm operation. synchronous operation operation that progresses only when a timi ng signal, known as a clock, transitions between logic levels (that is, at a clock edge). versatileio? (v io ) separate power supply or voltage reference si gnal that allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs. unlock bypass mode that facilitates faster program time s by reducing the number of command bus cycles required to issue a write operation command. in this mode the initial two unlock write cycles, of the usual 4 cycle program command, are not required ? reducing all program commands to two bus cycles while in this mode. word two contiguous bytes (16 bits) located at an even byte boundary. a double word is two contiguous words located on a two word bo undary. a quad word is four contiguous words located on a four word boundary. term definition
80 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary wraparound special burst read mode where the read address wraps or returns back to the lowest address boundary in the selected range of wo rds, after reading the last byte or word in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read words in the sequence 2, 3, 0, 1. write interchangeable term for a pr ogram/erase operation where the content of a register and or memory location is being altered. the term write is often associated with writing command cycles to enter or exit a particular mode of operation. write buffer multi-word area in which multiple words may be programmed as a single operation . a write buffer may be 16 to 32 words long an d is located on a 16 or 32 word boundary respectively. write buffer programming method of writing multiple words, up to the maximum size of the write buffer, in one operation. using write buffer programming re sults in greater than eight times faster programming time than by using single word at a time programming commands. write operation status allows the host system to determine the st atus of a program or erase operation by reading several special purpose register bits . term definition
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 81 preliminary
82 s29pl-n mirrorbit? flash family s29pl-n_00_a4 november 23, 2005 preliminary 14 revisions revision a0 (february 28, 2005) initial release revision a1 (august 8, 2005) performance characteristics updated package options mcp look-ahead connection diagram corrected pinout memory map added sector and memory address map for s29pl127n device operation table added dual chip enable device operation table v cc power up updated t vcs . added v cc ramp rate restriction dc characteristics updated typical and maximum values. revision a2 (october 25, 2005) ordering information updated table. connection diagram and package dimensions - s29pl-n fortified bga added pinout and package dimensions. global changed data sheet status from advance information to preliminary. removed byte address information distinctive and performance characteristics removed enhanced versatilei/o, updated read access times, and package options. logic symbol and block diagram removed v io from logic symbol and block diagram. erase and programming performance updated table. write buffer programming updated write buffer abort description. operating ranges updated v io supply voltages. dc characteristics updated i cc1 , i cc4 , i cc6 .
november 23, 2005 s29pl-n_00_a4 s29pl-n mirrorbit? flash family 83 preliminary revision a3 (november 14, 2005) ordering information updated table valid combinations table updated table revision a4 (november 23, 2005) logic symbols removed v io from the illustrations block diagram removed v io from the illustration connection diagrams modified fortified bga pinout (laa064) pl129n sector and memory address map updated address ranges for banks 2a and 2b colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and househol d use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reac tion control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that sp ansion will not be liable to you and/or any third party for any claims or damages ari sing in connection with above- mentioned uses of the products. any semiconductor device has an inherent chance of failure. you must protect against injury, da mage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prev ention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on ex- port under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion llc pro duct under development by spansion llc. spansion llc reserves th e right to change or discontinue work on any product without notice. the information i n this document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ?2005 spansion llc. all rights re served. spansion, the spansion logo, and mi rrorbit are trademarks of spansion llc. o ther company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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